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Questions tagged [active-hdl]

ALDEC Active-HDL™ is a Windows® based, integrated FPGA Design Creation and Simulation solution for team-based environments. Active-HDL’s Integrated Design Environment (IDE) includes a full HDL and graphical design tool suite and RTL/gate-level mixed-language simulator for rapid deployment and verification of FPGA designs.

ALDEC Active-HDL provides

  • Project Management
  • Graphical/Text Design Entry
  • Simulation and Debugging
  • Documentation in HTML/PDF

for FPGA design using mixed HDL languages with a common kernel mixed-language simulator (VHDL, Verilog, SystemVerilog (Design), SystemC).

This tag is intended for questions pertaining to Active-HDL unique features.

34 questions
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Converting VHDL logic vectors to user-defined strings for simulation

I'm using active-hdl to simulate my FPGA designs and I'd like to know if it's possible to use dynamically generated strings to represent my signals in the simulator. For example, let's say I have a 4-bit std_logic_vector containing an op-code, I'd…
Mark Feldman
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Signal initialization VHDL

I have an entity which has this TEMPERATURE: in STD_LOGIC_VECTOR(7 downto 0); as one of the inputs and I need a signal that has the initial value TEMPERATURE. In the entity architecture I've declared the signal signal temp:STD_LOGIC_VECTOR(7…
user9785232
3
votes
2 answers

Active-HDL simulation clock crossing

I have 2 modules using the same clock but in different files, when I sample signal that come from module A in module B , in the Waveform simulation it doesn't get samples after one clock cycle like it should , it shows that is samples in the same…
roeye
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1 answer

How to do simple Aldec Active-HDL simulation with waveform using Tcl scripting?

Having a simple test bench like: entity tb is end entity; architecture syn of tb is signal show : boolean; begin show <= TRUE after 10 ns; end architecture; ModelSim GUI allows simulation and waveform viewing with a Tcl script in "all.do"…
EquipDev
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2 answers

Aldec Active-HDL: vlib in GUI gives "Warning: Cannot create library" without usable library

From the Aldec Active-HDL GUI the vlib should create a work library, e.g.: vlib my_lib This creates a "my_lib" directory under the current directory, but with the warning: Warning: Cannot create library A subsequent set worklib my_lib fails with…
EquipDev
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1 answer

Why do I get run time fatal error - Range width expression must be positive - for my up counter design?

I am trying to design a 17-bit ripple up counter using a positive edge triggered d flip flop in my design. Here is my code: `timescale 1us/ 1ns module upcounter (clk, pr, clr, out); input wire clk; input wire pr; input wire clr; …
MD. SHAZZAD HOSSAIN
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Error: COMP96_0207: Tarea_MUX_39203394.vhd : (53, 2): No actual specified for local port "SEL"

library IEEE; use IEEE.std_logic_1164.all; entity Tarea_MUX_39203394 is port( A : in STD_LOGIC_VECTOR(1 downto 0); B : in STD_LOGIC_VECTOR(1 downto 0); C : in STD_LOGIC_VECTOR(1 downto 0); D : in STD_LOGIC_VECTOR(1 downto 0); …
SaLi MuGa
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1 answer

Why are modules not connected to each other?

I have to do Verilog coding in Active HDL 12, but I do not know why the three modules do not connect to each other in the top module. top module `timescale 1 ns / 1 ps module Main (Mx1,Mx2,Mx3,Mx4,My); input Mx1; input Mx2; input Mx3; input…
MohammadReza
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1 answer

Function to_hstring from std.textio is not working [VHDL]

I tried to run some code from Stack Overflow (How to write an integer to stdout as hexadecimal in VHDL?) and it turned out that to_hstring doesn't work (Even though std library is standard for VHDL). I am using Active-HDL 9.1 (probably the root of…
Петр Воротинцев
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1
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1 answer

Output array won't take the value of an array register

In a simple module I have defined a 4-bit array register, and I use it to assign a value to a 4-bit array output. The output acts like a 1-bit wire even if it has been defined as a 4-bit array. `timescale 1ns/1ps module test(input in, …
TomatoLV
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1
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1 answer

MachX03 library error in Active-hdl for fpga simulation

edit: I just reinstalled lattice diamond and the updates, Active-hdl was installed automatically, but the simulation still gives me the same error. when i change library machXO3; use machXO3.all; to library machXO2; use machXO2.all; it…
user169808
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1
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1 answer

How to use microsoft visual studio as default text editor in Active-hdl

I want to change default editor in Active-hdl to microsoft visual studio and every time I click on file in Active-hdl, vs-code open that file,How can I do that?
amin saffar
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1
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1 answer

viewing waveform- Active hdl

I am quite new to verilog and active-hdl. I have got a problem and I would appreciate it if someone could advise me on this. I can't see the waveforms of second layer modules on waveform viewer. More precisely, the signals in submodules show either…
M.X
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1 answer

SystemVerilog stringify (`") operator and line breaks

I'm using the SystemVerilog stringify operator, `", in a macro, as below. The case is deliberately contrived to show the bug: module my_test(); `define print(x) $fwrite(log_file, `"x`") `define println(x) $fwrite(log_file, `"x\n`") …
Eric
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1 answer

Elevator project in VHDL compiles, but doesn't work in the simulation

I am trying to make an elevator in VHDL, to be implemented on FPGA. It has 0-12 floors, it has buttons for up/down outside, depending on which direction you wish to go, and buttons inside. I am checking first if the outside buttons work, the…
Bogdan Marcu
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