Questions tagged [digital-design]
79 questions
8
votes
3 answers
AND all elements of an n-bit array in VHDL
lets say I have an n-bit array. I want to AND all elements in the array. Similar to wiring each element to an n-bit AND gate.
How do I achieve this in VHDL?
Note: I am trying to use re-usable VHDL code so I want to avoid hard coding something…
user3051199
8
votes
6 answers
Finding prime factors to large numbers using specially-crafted CPUs
My understanding is that many public key cryptographic algorithms these days depend on large prime numbers to make up the keys, and it is the difficulty in factoring the product of two primes that makes the encryption hard to break. It is also my…
Adam Batkin
- 51,711
- 9
- 123
- 115
4
votes
2 answers
How to think about digital circuit design
How does one go about thinking about designing digital logic chips in an abstract way?
I'm currently working through "The Elements of Computing Systems" I'm in the first chapter, and I've implemented the following gates, starting from…
afkbowflexin
- 4,029
- 2
- 37
- 61
3
votes
2 answers
"Warning C0007 : Architecture has unbound instances" issue!
I have the following source code from the CD attached with "Fundamental of Digital Design" book.
When I tried run the program, it gave me the following error:
Compiling Fig17_13.vhd...
C:\Users\SPIDER\Desktop\EE460\The Final…
Eng.Fouad
- 115,165
- 71
- 313
- 417
3
votes
1 answer
Sending data from slow clock domain to fast
Suppose I want to send a stream of data from a slow clock domain to a fast domain, and the latency is important. Is there some way of establishing a lower bound on the latency?
The standard solution is a FIFO, and its latency would provide a tight…
jeremiah
- 115
- 1
- 8
3
votes
1 answer
Verilog apply force to module output without changing internal state
In my testbench, I want to simulate a system condition by forcing a certain module's output in the RTL:
force DUT.driving_module.xx = 0;
But when doing this with the force command, the wire that drives the output inside the module is also forced,…
chinocolerico
- 97
- 2
- 12
3
votes
3 answers
How to detect the posedge of two clocks (asynchronous to each other) at the same time in verilog?
I am working on a design which should detect the first match of two rising edges of two asynchronous clocks of different frequencies.
code something like this may work for simulation.
fork
@posedge clkA
begin
a=$time
end
@posedge clkB…
Reddy
- 98
- 1
- 7
2
votes
1 answer
Why do we have to add a "clr" (clean input wire) while forming a T flip-flop in Verilog with Vivado?
I am trying to form a T flip-flop in Verilog. I am studying verilog from "Digital System Design with FPGA: Implementation using verilog and vhdl" and the code for T flip-flop is here below:
module t_flip_flop(t,clk,clr,q,qn);
input…
2
votes
1 answer
How to create K-MAP from function
How can I create a K-MAP by looking at this function.I dont know how to create one
Emirhan Selim Uzun
- 632
- 5
- 24
2
votes
1 answer
iverilog error: syntax in assignment statement l-value
I'm new to SystemVerilog, and I use Icarus Verilog.
I'm trying to design a simple FSM to practise, but I keep getting this error:
error: syntax in assignment statement l-value
module primoex (input logic clk, reset, x,
output logic…
Thomas Herondale
- 87
- 1
- 7
2
votes
0 answers
Proteus error:logic race conditions detected during transient analysis
I’m trying to design a simple alu that get two 5-bit number and return the result of adding them or subtract or multiply or divide.
With using ICs ,it goes well.However I want to design everything myself.
In designing divide I get error :
logic race…
Melika Z
- 21
- 3
2
votes
2 answers
Clock Domain Crossing for Pulse and Level Signal
For pulse we use Pulse-Synchronizer and for Level Signal we use 2-flop synchronizer but what if the signal can be of Pulse or Level behaviour. Is there any way to synchronize that?
Ishita Shah
- 99
- 1
- 4
- 12
2
votes
1 answer
Verilog code to compute cosx using Taylor series approximation
I'm trying to implement COS X function in Verilog using Taylor series. The problem statement presented to me is as below
"Write a Verilog code to compute cosX using Taylor series approximation. Please attach the source and test bench code of the…
Displayname
- 25
- 1
- 10
2
votes
2 answers
How 16 bit array needs 5 bit address (Xilinx Vivado HLS)?
I am novice in Xilinx HLS. I am following tutorial ug871-vivado-high-level-synthesis-tutorial.pdf(page 77).
The code is
#define N 32
void array_io (dout_t d_o[N], din_t d_i[N])
{
//..do something
}
After synthesis, I got report like…
Main
- 1,804
- 3
- 20
- 28
2
votes
2 answers
Converting six-bit binary number to it's corresponding two digit BCD number?
Here is the question that I tried so hard but I couldn't solve it.
I captured the question as it was from the question-paper, I couldn't solve it in the exam, and non of student's could.
You probably ask, why don't you ask your lecturer ( it's fair…
Caffe Latte
- 1,693
- 1
- 14
- 32