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In my testbench, I want to simulate a system condition by forcing a certain module's output in the RTL:

force DUT.driving_module.xx = 0;

But when doing this with the force command, the wire that drives the output inside the module is also forced, which leads to other parts of the system being also affected. What I really need is to force the output of the module, without changing its internal state, like this:

enter image description here

I can't modify the RTL code at all. Is there a way to achieve this from the testbench?

Paebbels
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chinocolerico
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1 Answers1

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When you have a port with a wire on both sides of the port connection, the wire gets collapsed into a single wire.

The way to do this is use logic instead of wire inside your module. The only place you should be using wire anywhere in SystemVerilog is if the signal has multiple drivers.

In Verilog, you can always make the output port of a module a reg

In either case, an output port that is a variable creates an implicit continuous assignment to whatever it connected to in the higher level module. Continuous assignments are uni-directional and a force will not propagate back into the module.

dave_59
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    In some simulators, if you add debug flags to your simulation build, it will not do the logical wire collapse. This works in VCS, afaik, and I think ncsim, or whatever Cadence is calling it this week. Then you can do a `force` or a `put` on the wire and it will only effect "downstream" wire. Not realistic modeling at all, but useful. – Ross Rogers Nov 13 '15 at 15:11
  • @dave_59 things in fact are a bit more complex. For simplicity's sake I didn't mention that my design is a netlist composed of primitives (mantaining the hierarchy of the original RTL design). So, the wires and its drivers are all defined by the synthesis tool. That's what I meant by "can't modify the code" – chinocolerico Nov 16 '15 at 12:35
  • Why is that you can ask a tool to modify the code for you, but you can't do it yourself? Of course you can modify the code, it's just a text file. – dave_59 Nov 16 '15 at 21:49
  • Well, of course I can just go ahead and modify the netlist, but it wouldn't be very neat - it's almost never a good idea to manually modify auto-generated code, if the design is re-compiled you have to do it again, no documentation, etc... – chinocolerico Nov 17 '15 at 22:28
  • I guess it depends on the original intent in using a `force` statement. If you are using it to debug an unknown problem, or to verify a potential fix, then the force is a temporary statement anyways. If you are doing this to _fast_ initialize a block of code, there might be other tool specific alternatives. – dave_59 Nov 17 '15 at 23:12