Digital logic is the representation of signals and sequencing of a digital circuit. It is the basis for digital computing. (Note: There is the Electrical Engineering Stack Exchange website which is more suited to asking questions on hardware.)
Questions tagged [digital-logic]
229 questions
24
votes
6 answers
Why were bitwise operations slightly faster than addition/subtraction operations on older microprocessors?
I came across this excerpt today:
On most older microprocessors, bitwise operations are slightly faster than addition and
subtraction operations and usually significantly faster than multiplication and division
operations. On modern…
Vilhelm Gray
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16
votes
3 answers
What to use for VHDL/digital-logic simulation on Mac OS X
I suddenly realized that there is no Altera Quartus or Xilins ISE or ModelSim on Mac OS X.
What do people use to at least simulate VHDL and schematic designs on Macs?
Vladimir Keleshev
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11
votes
10 answers
Linear feedback shift register?
Lately I bumped repeatedly into the concept of LFSR, that I find quite interesting because of its links with different fields and also fascinating in itself. It took me some effort to understand, the final help was this really good page, much better…
MattiaG
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10
votes
2 answers
How CPUs implement Instructions like MUL/MULT?
In different assembly languages MUL (x86)/MULT (mips) refer to multiplication. It is a black box for the programmer. I am interested in how actually a CPU accomplishes a multiplication regardless of the architecture. Lets say I have two 16-bit…
George
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9
votes
4 answers
What's included in a Verilog always @* sensitivity list?
I'm a bit confused about what is considered an input when you use the wildcard @* in an always block sensitivity list. For instance, in the following example, which signals are interpreted as inputs that cause the always block to be…
Frank Dejay
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7
votes
1 answer
How to handle loops in a digital logic simulator?
I'm developing a digital logic simulator to build my own CPU in it later (so it's a long term project). Everything works great for circuits with no loops, for example a fulladder. Then there are circuits like an SR latch, where one of the inputs of…
emre23
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6
votes
1 answer
Using 2's Complement to Perform Binary Division for Signed Number
First of all, this is not a duplicate question of this because it hasn't answered my questions below.
I searched for many resources and ended with no clear perception of how to perform signed number division using 2's complement, specifically for…
user2963216
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5
votes
2 answers
Digital Logic - Karnaugh Map
The initial problem starts like this. There are 6 states. At each state when w=1 move to the next state, when w=0 then stay at the current state. At each state display a number using a standard 7 led display (BCD). Those numbers are 8 -> 1 -> 9 -> 4…
CMacDady
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4
votes
1 answer
How to simulate output delay using next_trigger() in SystemC?
I have been reading this upvoted answer on Stack Overflow: https://stackoverflow.com/a/26129960/12311164
It says that replacing wait(delay, units); in SC_THREAD to next_trigger(delay, units) in SC_METHOD works.
But when I tried, it does not work. I…
user12311164
4
votes
2 answers
How does comparing the Sign and Overflow Flag determine operand relationships?
Jump's based on comparing signed integers use the Zero, Sign, and Overflow flag to determine the relationship between operands. After CMP with two signed operands, there are three possible scenario's:
ZF = 1 - Destination = Source
SF = OF -…
cafekaze
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3
votes
3 answers
Why K-map has states in sequence of 00,01,11,10 instead of 00,01,10,11?
Why K-map has states in sequence of 00,01,11,10 instead of 00,01,10,11?
Ashik Ghona
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3
votes
1 answer
Chisel3 REPL peek value is correct but expect fails in test
I am using Chisel3 to build my circuit, and I have the following test
reset()
private val inputData = IndexedSeq.fill(ProcedureSpaceSize)(0: BigInt)
.patch(0, Seq(63: BigInt), 1)
.patch(1, Seq(65: BigInt), 1)
.patch(2, Seq(98:…
apen
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3
votes
1 answer
How to use parameterized bitwidth for a constant value in Verilog?
Consider the following example:
parameter BITWIDTH = 16;
This works:
logic [1:0][BITWIDTH-1:0] var = {16'h30, 16'h40};
This doesn't work:
logic [1:0][BITWIDTH-1:0] var = {BITWIDTH'h30, BITWIDTH'h40};
How can I use parameters in the above line…
user3303020
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3
votes
2 answers
not a valid l-value - verilog compiler error
module fronter ( arc, length, clinic ) ;
input [7:0] arc;
output reg [7:0] length ;
input [1:0] clinic;
input en0, en1, en2, en3; // 11
// clock generator is here
g_cal A( en0) ;
g_cal B( en1) ;
g_cal C( en2) ;
g_cal D( en3) ;
always…
user478571
3
votes
1 answer
what is the operator precedence in Boolean algebra?
As a XOR b NOR c is not equal to a NOR b XOR c,there must be some precedence rule for all operators in Boolean algebra.So what is the precedence rule for XOR,NAND,XNOR,NOR ??
Dipak Koley
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