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I'm using the SystemVerilog stringify operator, `", in a macro, as below. The case is deliberately contrived to show the bug: 

module my_test();
    `define print(x) $fwrite(log_file, `"x`")
    `define println(x) $fwrite(log_file, `"x\n`")
    integer log_file;

    initial begin
        log_file = $fopen("result.txt", "w");
        `print(A);
        `print(B);
        `println(C);
        `println(D);
        `print(E);
        `print(F);
    end
endmodule

This gives the output (no trailing newline):

ABC
`D
`EF

Why are there `s in the output, but only from the println?
Is this documented behaviour in the spec, or a bug in my simulator (Aldec Active-HDL)?

dave_59
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Eric
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1 Answers1

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This is a bug in your tool. However, the second `" is not needed and gives you the results you are looking for.

dave_59
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  • Can you link me to an explanation of why that second `` `" `` is unnecessary? Preferably a page in the spec – Eric Sep 28 '17 at 05:15
  • There is only one page in the 1315 pages of the LRM that mentions `" and it mentions mixing. – dave_59 Sep 28 '17 at 12:35
  • I'm a little shocked how vague that description is - it says that the macro text can use a mixture, not specifically that a string literal can begin with one and end with the other. – Eric Sep 28 '17 at 15:25
  • It does go out of its way to say that if you start with the un-escaped double quote, the final quote could never be escaped because the back-tick would be considered part of the string literal and not an escape charactor. So the only mixture allowed is starting with an escaped-" and ending with a simple ". – dave_59 Sep 28 '17 at 16:54
  • That's possibly not restrictive enough. It might just mean that ```define macro {`"foo`", "bar"}`` is allowed. That's a mixture too. – Eric Sep 28 '17 at 17:01