1

I am trying to design a 17-bit ripple up counter using a positive edge triggered d flip flop in my design. Here is my code:

`timescale 1us/ 1ns 

module upcounter (clk, pr, clr, out);
    input wire clk;
    input wire pr;
    input wire clr;
    output wire [16:0] out;
    
    wire [16:0] fb;
    wire [16:0] i_wire;
    
    //const int n = 16;
    genvar i;
    
    //wire and1, and2;

    generate
    for (i = 0; i<17; i++) begin
        //int j = i;
        if (i == 0)begin
            dff d[i] (.clk(clk),.pr_b(pr),.clr_b(clr),.d(fb[i]),.q_b(fb[i]),.q(i_wire[i]));
        end else begin 
            dff d[i] (.clk(fb[i-1]),.pr_b(pr),.clr_b(clr),.d(fb[i]),.q_b(fb[i]),.q(i_wire[i]));
        end
        assign out[i] = i_wire[i];
    end
    endgenerate
endmodule

The code compiles without any error, but while initializing simulation it throws up a runtime fatal error saying Range width expression must be positive, it indicates the error occurs in the following line:

 dff d[i] (.clk(clk),.pr_b(pr),.clr_b(clr),.d(fb[i]),.q_b(fb[i]),.q(i_wire[i]));

How can I solve this error?

I'm using active hdl as the EDA.

I have tried using generate and endgenerate block.

toolic
  • 57,801
  • 17
  • 75
  • 117
MD. SHAZZAD HOSSAIN
  • 11
  • 1

1 Answers1

1

VCS generates this compile error:

Error-[ZONVS] Zero or negative value for size
Line 19
upcounter, "genblk1[0].i"
  Zero or negative value for size is not allowed.
  Value: 0
  Please fix the size value as a positive number.

When i=0, dff d[i] resolves to dff d[0], which the compiler does not like.

In that line, you can use d0 instead of d[i]:

        dff d0 (.clk(clk),.pr_b(pr),.clr_b(clr),.d(fb[i]),.q_b(fb[i]),.q(i_wire[i]));

That gets past the compile error. However, you end up with a lot more than 17 dff instances, which you probably don't want. For example, when i=4, d[i] resolves to d[4] which is an array of 4 instances.

You likely just want to use dff d on both lines. This gives you 17 dff instances.

toolic
  • 57,801
  • 17
  • 75
  • 117