Having a simple test bench like:
entity tb is
end entity;
architecture syn of tb is
signal show : boolean;
begin
show <= TRUE after 10 ns;
end architecture;
ModelSim GUI allows simulation and waveform viewing with a Tcl script in "all.do" with:
vlib pit
vcom -work pit tb.vhd
vsim pit.tb
add wave sim:/tb/show
run 20 ns
Where to do all.do
in the ModelSim GUI console will make library, compile, load tb model, and show the waveform:
How to make a similar simple Tcl script for a similar simulation with Aldec Active-HDL simulator ?