Why are modules not connected to each other?

Question

I have to do Verilog coding in Active HDL 12, but I do not know why the three modules do not connect to each other in the top module.

top module `timescale 1 ns / 1 ps

module Main (Mx1,Mx2,Mx3,Mx4,My);
input Mx1;
input Mx2;   
input Mx3;
input Mx4;
output My;

wire  interface1;
wire interface2;

And a1(.X (MX1),.Y (MX2),.O1 (interface1));
Or o1(.X1 (MX3),.Y1 (MX4),.O2 (interface2));
Xor x1(.X2 (interface1),.Y2 (interface2),.O3 (My));
   
endmodule

And module

`timescale 1 ns / 1 ps

module And ( X ,Y ,O1 );

input X ;
input Y ;
output wire O1 ;

    assign O1 = X & Y;

endmodule

Or module

`timescale 1 ns / 1 ps

module Or ( X1 ,Y1 ,O2 );

input X1 ;
input Y1 ;
output wire O2 ;

    assign O2 = X1 & Y1;

endmodule

Xor module

`timescale 1 ns / 1 ps

module Xor (X2,Y2,O3);

input X2;
input Y2;
output O3;

    assign O3 = X2 ^ Y2;

endmodule

In the output, I do not see an answer at all.

toolic · Answer 1 · 2021-11-22T18:17:54.087

Verilog is case-sensitive. This means Mx and MX are two different signals. The Mx input is not connected to the And module, for example. One way to fix it is to change:

And a1(.X (MX1),.Y (MX2),.O1 (interface1));
Or o1(.X1 (MX3),.Y1 (MX4),.O2 (interface2));

to:

And a1(.X (Mx1),.Y (Mx2),.O1 (interface1));
Or o1(.X1 (Mx3),.Y1 (Mx4),.O2 (interface2));

Some simulators generate warning messages. For example, the Cadence simulator (available on edaplayground) shows warnings such as:

And a1(.X (MX1),.Y (MX2),.O1 (interface1));
                      |
xmelab: *W,CSINFI : implicit wire has no fanin (Main.MX2).

Another way to help identify this type of common error is to use this compiler directive in your code:

`default_nettype none

Your simulator should generate compile errors in this case.

Why are modules not connected to each other?

1 Answers1