I have successfully setup a Cocotb verification environment for my design, and I am happy the way it works for RTL (VHDL in my case).
My design is using generics, and I am retrieving the value of these generics in several places of the python code (mostly in the run_test and in the model), following the template:
my_generic = dut.GEN_NAME.value
Unfortunately, this is not working in the case of gate level simulation, since my synthesized design does not have generics anymore, and therefore dut.GEN_NAME.value does not exist.
Should I move all in the direction of getting the parameters/generics values from the simulation flow (makefile of Cocotb) ?
If so, what is the cleanest way to do so? Using env variable?
(Btw, I use Questa, even if I don't expect this aspect to be simulator dependent...)
Thanks for your help and your advices...