MIPS is a common RISC (Reduced Instruction Set Computer) ISA (Instruction Set Architecture), one of the first of its kind, and early MIPS is still used as an example of a classic RISC 5-stage pipeline. MIPS originally stood for "Microprocessor without Interlocked Pipeline Stages", though modern MIPS implementations now have interlocked pipeline stages.

Stack Overflow's mips tag gets computer-architecture about MIPS-like simple CPUs, and assembly questions about programming it. In both cases, it's common to ask about simplified MIPS CPUs that don't use a branch-delay slot because that's what students are often working with, unlike actual commercial MIPS CPUs and the actual MIPS ISA. The MARS and SPIM simulators are configured by default to simulate a MIPS without branch-delay. (And the majority of MIPS assembly programming questions on Stack Overflow are about programming in that environment with their toy system calls as well, which implement things like print integer or read integer, things which on a real-world system would be done by C library functions.)

MIPS processors have two endianness flavours: both big-endian and little-endian (often referred to as mipsel), so it might be useful to apply one of those tags as well. Many common modern System-on-chip processors that run Linux and are often found in devices such as consumer routers / Wi-Fi devices, IP cameras and other embedded systems employ MIPS architecture, including many Broadcom, Atheros and Ralink SOC.

Overview:

• Wikipedia overview: history, CPU families, instruction format, register usage conventions
• MIPS 32 architecture: manufacturer summary and links to reference manuals
• MIPS 64 architecture: ditto for 64-bit CPUs (navbar has links for microMIPS, DSP ASE, MT, SmartMIPS, MIPS16, MIPS-3D, and MCU ASE)

Instruction set references:

• MIPS32™ Architecture For Programmers Volume II: The MIPS32™ Instruction Set is the name of the document that lists and describes all instructions in the MIPS32 instruction set, along with their encodings. It can be found through the MIPS 32 architecture link above, or through a search engine.

• MIPS64™ Architecture For Programmers Volume II: The MIPS64™ Instruction Set is the name of the same document for the MIPS64 instruction set.

• MIPS R3000 manual (MIPS I) from 1994. Chapter 9 includes an instruction-set table (including expansions for pseudo-instructions) and C syntax for what it does. Handy to see sequences for abs and neg, as well as which instructions are real machine instructions.

• See MIPS Run, especially Chapter 8. Complete Guide to the MIPS Instruction Set. Table 8.6 has encodings and when each instruction was introduced. (MIPS II, III, IV, and some special instructions on specific MIPS chips.) It includes TLB-maintenance instructions, MIPS II branch-likely instructions (branch-delay slot NOPed when not taken), and floating point (FP) instructions. It's a real book, so it has whole sections of explanation of how to use / how it works / why it makes sense for things like the unaligned-load instructions. But it doesn't have MIPS32 or anything newer than MIPS IV, it seems.

• Instruction-set quick reference: MIPS Green sheet from Patterson & Hennessy's textbook. This is quite good, but is not complete even for classic MIPS I integer instructions. It omits real machine instructions including at least bgezal, and even non-linking compare-reg-against-zero instructions bltz/blez/bgtz/bgez. This video by University of Illinois professor Geoffrey Herman walks through how to read the notation for what each instruction does, and what the machine encoding is.

Running / debugging MIPS assembly code:

University / college courses that involve MIPS assembly language programming often make use of MIPS simulators such as spim or mars-simulator to allow students to run their programs. These simulators include debugging features like single-stepping, breakpoints, and register/memory viewers, that helps developers understand the runtime behaviour of their code.

Before posting a question asking for debugging help you should attempt to debug your program yourself. Even if you're unsuccessful in finding the bugs, your initial debugging attempt will probably have helped you narrow down the potential problem sources, and get a better understanding of your own code. Your findings should be detailed in your question, so that people attempting to answer your question won't have to duplicate your work.

Useful / basic Q&As about assembly programming

• Reading and printing an integer in mips basic usage of MARS/SPIM integer input/output system calls, showing which registers they use.

• If/Else Statement on character strings from SPIM system calls - how to use the read-string MARS/SPIM system call.

• Can you use multiple BEQ statements in MIPS? - execution falls through labels, they're just markers. If you want to jump somewhere else, you need a j or branch instruction.

• MIPS if greater or equals to how a high-level if(condition) reg++ translates into assembly the conditional branches.

• what will be the corresponding structure of if..else in MIPS?

• Mips-Assembly beq and

• How can I implement if(x >= '0' && x <= '9') range checks like isdigit in MIPS? - Basic if/else structure. Double-condition using two branches, or the integer range-check trick using a subtract and unsigned compare.

• C to MIPS assembly while loop - C while(){} becomes assembly that's like a do{}while() with a branch to maybe skip the whole thing.

• How to do less than or equal in Assembly Language(MIPS)? (producing a boolean 0/1 output without necessarily branching) for various conditions that slt / sltu don't do directly.

Q&As about internal data-paths / CPU-architecture / ISA-design

• How does MIPS I handle branching on the previous ALU instruction without stalling?
• Why doesn't there exists a subi opcode for MIPS?
• MIPS 32-bit architecture: how can a register in a register file be read from and written to in the same clock cycle?
• Why are bgezal & bltzal basic instructions and not pseudo-instructions in MIPS?
• Data Hazards and stalls
• MIPS pipeline timing diagram
• Why are data forwarding and stall cycles more efficient than NOPs for dealing with load-use hazards?