Why doesn't there exists a subi opcode for MIPS?

Question

I am very new to Assembly language. I was reading about MIPS architecture and came to know that you have addi opcode but there is no subi opcode. Why don't we have a subi opcode?

Near-duplicate [What is the "relationship" between addi and subi?](https://stackoverflow.com/q/11981660). Some MIPS assemblers implement `subi` as a pseudo-instructions. (including the MARS simulator but not SPIM.) — Peter Cordes, Nov 18 '18 at 13:35

score 23 · Accepted Answer · edited Apr 19 '12 at 08:40

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When you create an instruction set, you're bound by some constraints, such as the total number of instructions you can create. The MIPS creators realized that there isn't a need for subi (because you can add a negative number with addi using 2's complement), and they simply made the decision to forego making that instruction. It may have been to conserve the number of instructions, or just simply because it isn't needed.

edited Apr 19 '12 at 08:40

apaderno

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answered Aug 02 '11 at 20:43

Chris Gregg

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Thanks a lot. So they followed there rule, i.e "Less is more." – Aug 02 '11 at 20:45
@JustAnotherProgrammer - that's probably the case. Good luck with MIPS! [Patterson and Hennessy](http://www.amazon.com/Computer-Organization-Design-Fourth-Architecture/dp/0123744938/ref=sr_1_1?ie=UTF8&qid=1312318028&sr=8-1) is a great book for learning computer architecture (the bible), and the [SPIM simulator](http://spimsimulator.sourceforge.net/) is a decent tool if you want to practice your MIPS assembly. – Chris Gregg Aug 02 '11 at 20:51
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Why is 'sub' needed then? Can't we use 'add' to do any 'sub' operation by taking 2's complement – da4kc0m3dy Jul 27 '14 at 18:30
@mskd96 Yes, you could perform a `sub` that way, so it is not strictly necessary. But, unless there is another important operation that would be omitted from the ISA by including `sub`, it isn't detrimental to include it in the ISA. – Chris Gregg Jul 29 '14 at 13:57
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@mskd96 you forgot 1 of Patterson and Hennessy's design principles: *"Make the common case fast"*. `sub` is much more common than `subi` with immediates larger than 32767 so that'll why the instruction was introduced, otherwise we can have a complete instruction set with [only 1 instruction](http://en.wikipedia.org/wiki/One_instruction_set_computer) and also very slow to do common things. "Good design demands good compromises" – phuclv Nov 13 '14 at 04:10

score 4 · Answer 2 · answered Aug 02 '11 at 22:25

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Both addi and addiu take 16-bit signed immediates as operand, so it makes no sense to add separate subi and subiu opcodes.

answered Aug 02 '11 at 22:25

ninjalj

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They could easily have added a subi opcode to the assembler that maps to the same hardware instruction. – Bo Persson Aug 03 '11 at 09:12
@Bo Any decent MIPS assembler does support subi mnemonic (which emits addi). – Igor Skochinsky Aug 03 '11 at 09:52
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@Bo Persson: then it wouldn't be an opcode, but a pseudo-instruction :) – ninjalj Aug 03 '11 at 14:05
Just a question: is immediate in `addi` sign-extended when being added to a register? – user35443 May 31 '15 at 11:03
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@user35443: yes, also for `ADDIU` (`ADDIU` only differs from `ADDI` in that it does not raise Overflow Exceptions) – ninjalj May 31 '15 at 12:48

Why doesn't there exists a subi opcode for MIPS?

2 Answers2