I have a situation where I need to package a SystemVerilog environment and export it to a customer. I need to make sure I provide as few +incdir+
as possible for the customer to compile.
The environment is huge, and it contains many IPs and hence there are lot of directories that need to be included.
I want to know if there is any easy way to add incdir for compilation that includes directories of all the IPs?
I was thinking of add a file abc.txt
in each of the IPs that contain +incdir and having a top.txt that includes all the abc.txt from all the IPs. It did not work.
This is what I tried
f: abc.txt
+incdir+tb_top.sv
+incdir+ip1/abc.txt
+incdir+ip2/abc.txt
f:ip1/abc.txt
+incdir+a.sv
+incdir+b.sv
f:ip2/abc.txt
+incdir+a.sv
+incdir+b.sv