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Questions tagged [cadence]

A global provider of Electronic Design Automation (EDA) software and engineering services. It produces software for designing integrated circuits (also known as "chips"), and printed circuit boards.

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109 questions
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Sublime text: Adding symbols to a new language definition (syntax highlighting)

I have written syntax highlighting for a slightly unfamiliar language (Cadence SKILL) in sublime text 2. Its working like a charm, however I miss the feature of CTRL + R , which locates all the symbols (functions) in the present file in an easily…
deowood
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How can we add functional coverage while running simulation using NCSIM

I am trying to run a coverage regression using the NC tool from Cadence. I can see RTL coverage, but functional coverage in the scoreboard is missing. How can I add this scoreboard to the covdut option in NCSIM arguments? The scoreboard contains…
silentNinJa
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Web(GUI) based workflow platform for multi-tenant model

I'm looking at creating a web-based workflow platform that meets the following requirements. A workflow is a DAG of steps available in the user interface and can be stored as a JSON or YAML Steps: Tasks or functions,  can take input as well as…
satish mishra
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How to understand which SystemVerilog is supported by Cadence XMVLOG compiler?

I need to move my SV simulation environment from Questa to Xcelium 20.9. I'm facing problems compiling my files with xmvlog, while there are no issues with vlog. So here's what I did. Make sure the toolchain is correctly installed: I ran this…
a_bet
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Automate Interactive session using script

I need to run interactive software in parallel to an another software. This interactive software (Cadence) runs on a separate terminal. Using Matlab, I want to invoke a csh script that gives certain commands to this interactive session, which is…
Aksh Chordia
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Passing C structs through SystemVerilog DPI-C layer

SystemVerilog LRM has some examples that show how to pass structs in SystemVerilog to\from C through DPI-C layer. However when I try my own example it seems to not work at all in Incisive or Vivado simulator (it does work in ModelSim). I wanted to…
user3716072
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Make HTTP request from Cadence SKILL program?

Is it possible for Cadence SKILL code to make an HTTP request? If so, how? I have Googled and read the SKILL manuals I can find with no clear answer. I found this integration with a Python program which suggests that external programs can be called.…
Jonathan Eunice
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Toggle Coverage not getting collected

I am using a Coverage Configuration file to collect code coverage explicitly by mentioning "select_coverage -block -expression -toggle -module dut..." Somehow, I am not able to get any number on toggle coverage for the dut. I even tried using…
Shweta Saxena
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Communicating with Program by command line using Python

I am trying to create a python script that will allow some interface with Cadence Skill (command line interface). I want any output to be directed to the shell. I feel like this should be simple, but I'm not able to get it working yet. With Popen…
digitaLink
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How to parallel multiple run with ncverilog?

I would like to run parallel multiple run ncverilog. Normally, we use ncverilog run script like this. Run.scr- ncveriog blar~blar~ But this is run at once. It means that if I want to run 100 scripts , I have to run new after previous script end.…
bural
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Cadence Virtuoso Layout L phantom objects

I have a cell (call it A) which is used once in a hierarchically higher cell (call it P). When I place A in P, its borders are rather larger than the actual content of A. When I descend to A and zoom-fit, it is way zoomed out, indicating there is…
user3594792
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Setting Probes for SimVision in Verilog Code

I am working on simulations of verilog builded digital logic and need to restart a simulation very often to see the changes. I am using Cadence SimVision to review the waveforms. Is there a way to write commands in verilog for the SimVision…
Johannes
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TCL script not working anymore

I used to run a tcl script for the Cadence tools on a server, however, now the script fails to run. The script is based on the following one: #### Template Script for RTL->Gate-Level Flow #### all basic steps except for DFT-scan #### Fill in the…
Deadlock
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connecting VHDL port to system verilog interface definition in UVM

I am having this issues in the Cadence tool chain simulation when I try to connect the multidimensional user defined type in VHDL to SystemVerilog in a UVM environment. This is the VHDL output type definition: TYPE loop_reg_ty IS RECORD …
user2293385
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Get internal signals of vhdl design in ncvhdl (alternative to modelsim's signal spy)

In ModelSim you can use something like in modelsim we can use init_signal_spy("../.../sig", mysignal); to get deep hierarchy signals. Is there a way to get such signals with Cadence's NCVhdl? This should be flagged "SimVision", which is the name the…
Sadık
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