Best way to access the uvm_config_db from the testbench?

Question

I want to create a clock in my top level testbench whose period can be controlled from the test. What I did was set the period into the uvm_config_db and get it back in the testbench. I had to put in a #1 to make sure that the build phase was finished, otherwise the get returned the wrong value:

module testbench_top;
  int clk_period;

  bit clk = 0;

  initial begin
    #1;    
    void'(uvm_config_db #(int) ::get(null, "uvm_test_top.env", "clk_period", clk_period));
    // Create clk
    forever begin
      #(clk_period/2) clk = !clk;
    end
  end

I am annoyed by the #1. Is there a better way to check that the config has been set? Can I somehow block until start_of_simulation_phase?

nguthrie · Accepted Answer · 2014-02-28T20:08:32.283

14

I found it buried in the class reference: You can access the global singleton versions of each phase with <phase name>_ph. Then I can use the wait_for_state function to block until the start of the start of simulation phase. Simulated and it seems to work:

module testbench_top;
  int clk_period;

  bit clk = 0;

  initial begin
    start_of_simulation_ph.wait_for_state(UVM_PHASE_STARTED);    
    if(!uvm_config_db #(int) ::get(null, "uvm_test_top.env", "clk_period", clk_period))
      `uvm_fatal("CONFIG", "clk_period not set");
    // Create clk
    forever begin
      #(clk_period/2) clk = !clk;
    end
  end

edited Feb 28 '14 at 20:08

answered Nov 09 '13 at 19:34

nguthrie

2,615
6
26
43

I think you can use `wait(uvm_config_db #(int) ::get(null, "uvm_test_top.env", "clk_period", clk_period));` In the above answer how will one know if the config_db get fails ?? – Vineeth VS Feb 28 '14 at 14:37
@VineethVS good point: I will edit the answer to add `uvm_fatal if this get fails. – nguthrie Feb 28 '14 at 16:59

score 4 · Answer 2 · answered Nov 23 '13 at 11:19

4

Another alternative that can help is wait_modified function of uvm_config_db... Here is the excerpt from uvm reference manual

wait_modified:

static task wait_modified(uvm_component cntxt,
                          string  inst_name,
                          string  field_name)

Wait for a configuration setting to be set for field_namein cntxtand inst_name. The task blocks until a new configuration setting is applied that effects the specified field.

answered Nov 23 '13 at 11:19

siva008

99
6

Thankful for the suggestion. I will look into how this works. Not sure this perfectly addresses my problem since it is possible that the configuration could be changed multiple times before the simulation starts and I want to be sure to use the final value. – nguthrie Nov 24 '13 at 13:28

Best way to access the uvm_config_db from the testbench?

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