1Hz clock for a D FlipFlop VHDL

Question

I am trying to implement a 1hz clock for a D flipflop in VHDL.

Below is my code:

entity d_flip_flop is
    Port ( clk : in  STD_LOGIC;
           D : in  STD_LOGIC;
           Q : out  STD_LOGIC);
end d_flip_flop;

architecture Behavioral of d_flip_flop is
signal clk_div: std_logic; --divided clock
begin

--process to divide clock
clk_divider: process(clk) --clk is the clock port
variable clk_count: std_logic_vector(25 downto 0) := (others => '0');
begin
    if clk'event and clk = '1' then
        clk_count <= clk_count+1;
        clk_div <= clk_count(25);
    end if;
end process;

--main process  
main:process(clk_div)
    begin
        if clk'event and clk = '1' then
            Q <= D;
        end if;
end process;


end Behavioral;

But when I tried to compile it, the following error is reported:

ERROR:HDLParsers:808 - "F:/EE4218/XQ/d_flip_flop.vhd" Line 47. + can not have such operands in this context.

I have checked with several reference for the syntax and found nothing wrong with it. Can anyone point out the cause of the error ?

Thanks in advance!

possible duplicate of [Problem adding std\_logic\_vectors](http://stackoverflow.com/questions/4042832/problem-adding-std-logic-vectors) — John Dvorak, Feb 03 '13 at 07:44
This was the fourth hit on Google searching for the exact error message (#1 and #3 referred to std_logic). — John Dvorak, Feb 03 '13 at 07:48

score 1 · Answer 1 · answered Feb 03 '13 at 11:21

clk_count is being used to represent a number, not a bag of bits.

So use the type system instead of fighting it, and declare it as a number or at least some numeric type.

The best tool for this purpose, since you need to extract a bit from it, is numeric_std.unsigned.

So add use ieee.numeric_std.all;after the library ieee; clause, declare it as

variable clk_count: unsigned(25 downto 0) := (others => '0');

and you are done.

Martin Thompson · Answer 2 · 2013-02-05T17:25:02.803

1

Brian has the best answer, for powers-of-two anyway. Arguably, for other wrap around values, you should also use an integer for clock_count and wrap it:

signal clk_div : std_logic := '0';

clk_divider: process(clk) --clk is the clock port
subtype t_clk_count: integer range 0 to 12345678; -- for example
variable clk_count: t_clk_count := 0;
begin
    if clk'event and clk = '1' then
        if clk_count+1 >= t_clk_count'high then
           clk_div <= not clk_div;
           clk_count <= 0;
        else
            clk_count <= clk_count+1;
        end if;
    end if;
end process;

edited Feb 05 '13 at 17:25

answered Feb 05 '13 at 14:36

Martin Thompson

16,395
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My preference is also for integer (so I said "declare it as a number or ...") , even though you then have to code the wrap-round behaviour explicitly. But for this application where power-of-2 overflow is wanted, I went for the simpler answer. +1 for going the extra mile. – Feb 05 '13 at 15:02

score -1 · Answer 3 · answered Feb 03 '13 at 08:57

-1

In process clk_divider modify the following line:

clk_count <= clk_count +1;

to

clk_count := std_logic_vector(UNSIGNED(clk_count) + 1);

This is because clk_count is defined as a variable of type 'std_logic_vector'.

answered Feb 03 '13 at 08:57

Praveen Felix

1,408
9
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He will also need to add "use ieee.numeric_std.all" after "library ieee"; – Feb 03 '13 at 09:40
That's a quick hack (or Verilog users') fix IMHO – Martin Thompson Feb 05 '13 at 17:25

1Hz clock for a D FlipFlop VHDL

3 Answers3