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module circuit_1 (a, b, c);
input [1:0J a,b;
output [3:0J c;
assign c = a + b;

If input a = 2'b11 and input b = 2'b10,

what value would output c have ? Please give a descriptive answer.

Also kindly tell me functionality of assign and always. I am a bit confused.

Morgan
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user1104334
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  • This is more of a [Binary Mathematics](http://en.wikipedia.org/wiki/Binary_number#Addition) question. Please read the [wikipedia](http://en.wikipedia.org/wiki/Binary_number#Addition) page then update the question with your proposed answer. – Morgan Mar 25 '13 at 08:12
  • RE assign and always, the Q&A Format here does not lend itself well to additional questions. You can ask a new question but the answer will likely be check out the [LRM - Language Reference Manual - SystemVerilog 2012](http://standards.ieee.org/getieee/1800/download/1800-2012.pdf) Particularly section 10, Assignment statements starting on page 196. – Morgan Mar 25 '13 at 09:07

2 Answers2

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c = 4'b0101      // Output, implicitly a wire

"assign" is used for net type declarations(Wire,Tri etc).Since wires change values according to the value driving them, whenever the operands on the RHS changes,the value is evaluated and assigned to LHS(simulating a wire)

always - is used for registers + combinational logic. If it is always(@ posedge clk)- The event posedge clk triggers the always block and the logic inside the block is evaluated and assigned.

always @ (*) - If something in the RHS of the always block changes,that particular expression is evaluated and assigned.

Imagine assign as wires and always blocks as registers (For now) , as their behavior is same.

chitranna
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    `always @*` is for `reg` types not registers, `assign` implies the same combinatorial logic as `always @*`. `always @(posedge clk)` implies flip-flops (registers). – Morgan Mar 26 '13 at 07:40
  • My bad.. I knew it but failed to explain it – chitranna Mar 26 '13 at 10:30
  • No problem, you can edit you answers to improve it if you wish. – Morgan Mar 26 '13 at 10:44
  • @Morgan If `assign` implies the same combinational logic as `always @*` why do I have to use reg-variables for the always-block and wires for the assign? Why can't I use the wires for the always-block too? – GURKE Aug 04 '20 at 11:54
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    @GURKE because that is not valid syntax. reg was intended to mean flip flop, but the combinatorial usage messed that up. Modern versions of verilog (ie SystemVerilog) you can use `logic` instead, for all uses except multi driven wires. I think this is a pretty good answer: https://stackoverflow.com/a/33462996/97073 An external reference: https://blogs.mentor.com/verificationhorizons/blog/2013/05/03/wire-vs-reg/ – Morgan Aug 04 '20 at 14:48
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c = 0101, actually c[2:0] become 101 but extension of 0 takes place as c is a 4 bit data.

Yathati Sankeerth_8229
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