Synthesis warning in VHDL multiplier code

Question

When I synthesize this 32-bit multiplier code, I do not get any errors, just warnings that my input is not used and is assigned but not used. My code is this:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity multiplier is
    Port ( multiplicand : in  STD_LOGIC_VECTOR(31 downto 0);
           multiply : in  STD_LOGIC_VECTOR(31 downto 0);
           clk : in  STD_LOGIC;
           product : out  STD_LOGIC_VECTOR(63 downto 0));
end multiplier;

architecture Behavioral of multiplier is

    component adder32bit is
        port(addone, addtwo : in STD_LOGIC_VECTOR(31 downto 0);
                sum : out STD_LOGIC_VECTOR(31 downto 0);
                cout : out STD_LOGIC);
    end component;

    signal tempsum : STD_LOGIC_VECTOR(31 downto 0);
    signal preg : STD_LOGIC_VECTOR(63 downto 0);
    signal start : STD_LOGIC := '1';
    signal tempcout : STD_LOGIC;
    signal counter : integer := 1;
begin

    addN: adder32bit port map(multiplicand, preg(63 downto 32), tempsum, tempcout); 

    process(clk)
    begin
        if(rising_edge(clk)) then
            if(start = '1') then

                if(counter = 1) then
                    preg <= "00000000000000000000000000000000" & multiply;
                end if;

                if(preg(0) = '1') then
                    preg(63 downto 32) <= tempsum;
                    preg <= tempcout & preg(63 downto 1);
                else
                    preg <= '0' & preg(63 downto 1);
                end if;

                counter <= counter + 1;

                if(counter = 33) then
                    product <= preg;
                    start <= '0';
                    counter <= 1;
                end if;

            end if;
        end if;
    end process;

end Behavioral;

When I run the simulation, no matter what my two inputs are (multiplicand and multiply) the output will be like this: "0000...UUUUUUU"

Any suggestions as to what I should do here?

After one cycle, is "preg" the value you expect? If not, learn about the delta cycle model, and the sequencing of signal assignments in processes, figure out why not, and try again. This Q/A may be useful : http://stackoverflow.com/questions/13954193/is-process-in-vhdl-reentrant/13956532#13956532 — , Apr 22 '13 at 17:03
Hey thanks a lot, I found out the problem. The problem was that I was setting preg too many times in the process so it only took the last one. However.... now my problem is that how do I initialize preg so that the value of preg is "000... & multiply" ? my simulation only worked when I set preg to some actual value without using multiply. So can I use multiply to initialize preg in the signal line ? — user2308179, Apr 22 '13 at 17:59

score 0 · Answer 1 · answered Apr 22 '13 at 19:52

One way to initialise preginvolves just a minor change to your code...

            if(counter = 1) then
                preg <= "00000000000000000000000000000000" & multiply;
            else
               if(preg(0) = '1') then ...
            end if;

Synthesis warning in VHDL multiplier code

1 Answers1