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a beginner's question here.

I want to perform following operation,

I have a std_logic_vector(1 downto 0) input. And I should extend it to four bits;

like 11 => 0011

or 10 => 0010

I tried this but it failed.

(Data0 is declared as input at entity port list)

Signal Data0_4bit: std_logic_vector(3 downto 0) :=B"0000";

Data0_4bit(1 downto 0)<=Data0(1 downto 0);

Thanks in advance.

user2489165
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3 Answers3

5

VHDL won't allow that because you're attempting to double-assign the bottom two bits of Data0_4bit (Once in the declaration, and again when you assign them Data0).

Try the concatenation operator to assign the entire vector in a single operation:

Signal Data0_4bit: std_logic_vector(3 downto 0) := B"00" & Data0(1 downto 0);

Alternately, you can split the assignment into two lines:

Signal Data0_4bit: std_logic_vector(3 downto 0);  -- note that Data0_4bit is only declared here, not assigned a value
Data0_4bit(3 downto 2) <= B"00";                  -- assign top two bits to 0
Data0_4bit(1 downto 0) <= Data0(1 downto 0);      -- assign bottom two bits to Data0

Disclaimer: it's been 10 years since I've written VHDL, and I don't have a way to test that code.

Drew Shafer
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  • Syntax error has gone. Thanks Drew! I didn't do any simulation to test it yet but hopefully it will be working. – user2489165 Jun 15 '13 at 16:20
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You can use the resize function which is defined in the numeric std package for signed and unsigned types:

    use ieee.numeric_std.all;
    (...)
    Data0_4bit <= std_logic_vector( resize(unsigned(Data0), Data0_4bit'length)); --
cycodad
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More generically:

signal Data1: std_logic_vector(M downto 0);
signal Data0: std_logic_vector(N downto 0); -- N < M

data1(data0'range) <= data0;
data1(data1'high downto data0'length) <= (others => '0');

Or use a shift function shift a std_logic_vector of n bit to right or left

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