Program to create a Verilog block diagram

Question

I want to create a program to parse Verilog and display a block diagram. Can someone help me regarding what algorithms I need to look into? I found a good Verilog parser, but now I need to find the relation between each block and place them accordingly. It does not have to be extensively optimized.

UPDATE:

for now I am using ironPython to draw the block diagram in Visio.

Create a list of blocks with their inputs and outputs
Create a graph which matches all the outputs of a block to their corresponding inputs. This basically has all the connections between blocks.
Find a place for them in the Visio diagram.
Draw them on Visio
Connect them on Visio.

Is it possible for you to use vivado by xilinx, it already does it for you. — alex_milhouse, Jul 30 '13 at 21:30
No i have to create a visio diagram. Which is then easier to modify for future use. — user591124, Jul 31 '13 at 17:46

score 7 · Answer 1 · answered Jul 31 '13 at 13:18

Yosys is an open source verilog synthesis tool. It can also be used to analyze designs and create schematics (using GraphViz). See the screenshots on the webpage:

http://www.clifford.at/yosys/screenshots.html

If I understand your requirements correctly, Yosys already does what you want. If you still want to write your own program, you could use Yosys as a reference to get you started.

(Conflict of Interest Disclosure: I am the author of Yosys.)

score 1 · Answer 2 · answered Jul 30 '13 at 21:54

1

You could try using the Altera synthesis too, EASE, HDL designer, Synplify HDL Analyst, nSchema, or Xilinx PlanAhead.

answered Jul 30 '13 at 21:54

Veridian

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and now vivado by xilinx – alex_milhouse Jul 31 '13 at 18:50

score 0 · Answer 3 · edited May 23 '17 at 12:30

If you just want a viewer for blocks and their relationship, you can try Graphviz. An example you can found from another StackOverflow thread. You can simply parse the HDL design and build the relation of them, then write out to text format in Graphviz syntax. Then call the program to generate the

If you want to implement an advanced viewer, for example, it can zoom in/out, pan, jump into/out block, and selection, that's another story.

Program to create a Verilog block diagram

3 Answers3