difference between blocking and non blocking statements with intra-assignment delay

Question

What is the difference between the following 2 snippets of verilog code?

1)

always@(in)
  out = #5 in;

AND

2)

 always@(in)
   out <= #5 in;

Considering no other lines are present in the always block, can there be any difference in output? question is in reference to slide 16 (see o5 and o6 outputs) http://www.sutherland-hdl.com/papers/1996-CUG-presentation_nonblocking_assigns.pdf

score 3 · Answer 1 · answered Aug 27 '13 at 17:27

out = #5 in; blocks the next operation for 5 time units. It will prevent the monitoring of the next @(in) until the the 5 time units have passed. If you add a $display statement just before and after the assignment you will see 5 time units has passed.

always @(in) begin
    $display("enter @ %0t",$realtime);
    out = #5 in;
    $display("exit @ %0t",$realtime);
end
/*******************
 * Example output:
 * enter @ time 10
 * exit @ time 15
 *******************/

out <= #5 in; schedules the assignment of occur 5 time units in the future and allows the next operation to begin without waiting for assignment to complete.

always @(in) begin
    $display("enter @ %0t",$realtime);
    out <= #5 in;
    $display("exit @ %0t",$realtime);
end
/*******************
 * Example output:
 * enter @ time 10
 * exit @ time 10
 *******************/

Working example at the EDA Playground: http://www.edaplayground.com/s/6/114

Thank you for that explanation, it helped! Related question : Is `#5 out = in;` EXACTLY the same as `#5 out <= in;` ? I tried it out using your edaplayground example, and they seem to give the same entry-exit times (and also the same waveforms for `out`). However I was wondering if there is some other difference. — dhrumeel, Apr 13 '14 at 08:34
A delay in-front of a statement is always considered an blocking statement. Basically Verilog infers a semicolon; `#5 out ...` is the same as `#5; out ...`. Blocking (`=`) and non-blocking (`<=`) differences still apply: http://stackoverflow.com/questions/4653284/how-to-interpret-blocking-vs-non-blocking-assignments-in-verilog — Greg, Apr 14 '14 at 18:32

score 1 · Answer 2 · answered Aug 27 '13 at 14:43

They produce different output when in toggles before the #5 delay is up. The non-blocking assignment will always delay in by #5 regardless of how fast in toggles.

Examples on EDA Playground. Note the difference in sim output.

difference between blocking and non blocking statements with intra-assignment delay

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