Concurrent signal assignment in VHDL

Question

I was thinking about the signal assignment in generally and I got into a dilemma.

If I have some project in which I have the following code:

ARCHITECTURE wait_example of wait_example IS
SIGNAL sendB, sendA : std_logic;
BEGIN

sendA <= ‘0’;

A : PROCESS
BEGIN
-- something
END PROCESS A;

B : PROCESS
BEGIN
-- something
END PROCESS B;

C : PROCESS
BEGIN
-- something
END PROCESS C;

And so on... I was thinking about when will the "sendA <='0';" part occurs? Only once in the beginning? Will it constantly reset sendA to 0? Or something else?

Thanks in advance, Bojan Matovski

score 2 · Answer 1 · answered Sep 10 '13 at 09:20

2

Any concurrent statement has an equivalent process. Without a signal on the right hand side it's equivalent is a process terminated by a WAIT; statement. It'll execute once.

answered Sep 10 '13 at 09:20

Morten Zilmer · Accepted Answer · 2013-09-10T17:54:34.160

2

In addition to David Koontz good answer, it may be added that even through the sendA <= '0' is only executed once, it will continuously drive sendA to '0'. In test bench design, the final value on sendA is given by the resolution function over all drives of sendA, where as in synthesizable design there should not be multiple drivers.

If you also try to drive sendA from one of the processes like:

sendA <= '0';

A : PROCESS
BEGIN
  wait for 100 ns;
  sendA <= '0';
  wait for 100 ns;
  sendA <= '1';
  wait for 100 ns;
  sendA <= 'Z';
  wait;
END PROCESS A;

Then you will get the final value of sendA as:

0 ns: 'U', as result of resolution by '0' and 'U' from the yet unassigned signal driven in A process.
100 ns: '0', as result of resolution by '0' and '0'
200 ns: 'X', as result of resolution by '0' and '1'
300 ns: '0', as result of resolution by '0' and 'Z'

Waveform is shown below.

enter image description here

edited Sep 10 '13 at 17:54

answered Sep 10 '13 at 10:48

Morten Zilmer

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That means that sendA<='0'; on a Gateway level is something like connecting the signal to a ground. Wouldn't that mean that I could never get it on high? Just as you showed in the example: "It's U, then 0, then X, then 0, but never 1". Thanks for the answers for both. – Бојан Матовски Sep 10 '13 at 14:50
In gate-level design (synthesizable) you should not have multiple drivers, since the tools will normally report this as an error, as they can not determine the final value. The example above with value resolution only applies to test bench design. – Morten Zilmer Sep 10 '13 at 17:52
1

To find a confluence describing simulation cycle, drivers, and propagation of signal values you pretty much have to look in the IEEE Standard (e.g. IEEE Std 1076-1993, 12.6 Execution of a model). The standard is intended primarily for tool implementors and advances language users requiring authoritative explanation. [VHDL driving signal from different processes](http://stackoverflow.com/questions/9084975/vhdl-driving-signal-from-different-processes) demonstrates you can successfully understand the issues involved simply keeping in mind you're modeling hardware. – Sep 10 '13 at 19:31
OK, but I still keep my question about setting sendA to zero like above and then somehow setting it to one, when needed. Something like, when some control signal, for instance, appears and that activates some process in which I would like to change the value of the sendA signal to one. Is there anyway to do that? Should I use the same control signal for driving sendA to zero, but only when it has the opposite value? – Бојан Матовски Sep 12 '13 at 06:59
@Бојан Другар Матовски: Sounds like you should simply drive sendA from a single process or expression, based on whatever control signals you need. – Morten Zilmer Sep 12 '13 at 10:13
@MortenZdk, yes but what if I want to set SendA only once on zero for instance? Though I guess I can use some control signal withing the process to make that. – Бојан Матовски Sep 12 '13 at 13:16

score 1 · Answer 3 · edited May 23 '17 at 12:11

Although VHDL is a hardware description language, what you write down is a little different to the real circuit.

Concurrent assignments generally stand for combination logic. But that doesn't mean that you can't modify sendA's value after you make a concurrent assignment like sendA <= '0';, as MortenZdk mentioned. The value of signals with type std_logic are determined by a function called resolved function because std_logic is a resolved type. For example, if sendA has two drivers associated with it(sendA <= '0'; & sendA <= '1'; in two different processes), it'll get a 'X' eventually.

EDIT:
See also about delta time and multiple drivers.

Concurrent signal assignment in VHDL

3 Answers3