Regarding a constant in verilog

Question

I was going through a piece of verilog code and came accross the following

abet_val<=strt?{{12 -1{1'b0}}, write_rly}:{{12 -1{1'b0}}, 1'b1};

what does the stuff inside the curly braces "{}" mean? Please help me out.

Possible duplicate: http://stackoverflow.com/questions/2102746/what-do-curly-braces-mean-in-verilog — Neil Forrester, Sep 11 '13 at 13:07
...and note that '12-1' is evaluated as an expression in both places, so it's '11'. — EML, Sep 11 '13 at 13:52

score 0 · Answer 1 · answered Sep 11 '13 at 16:36

0

it is a mux between {11'b0}, write_rly and 12'b1 . when strt is a one you pick the first option and when it is a zero you get the second output

{} these are the concatenation operator meaning you combine them to make one number

answered Sep 11 '13 at 16:36

alex_milhouse

1 Answers1