How do I instantiate two modules with one module in Verilog?

Question

How can I instantiate copies of two different modules by a third module?

module instantiate (modx, mody);
  // ?  
endmodule

Answer 1

Just instantiate them. add instantiated twice with block names of add_0 add_1. for different modules just instantiate them as you would a your main block in a testharness.

module add(
  input      [31:0] i, //32 bit unsigned
  input      [31:0] j, //32 bit unsigned 
  output reg [31:0] y  //32 bit unsigned
); 

  always @* begin
    y = i + j;
  end

endmodule

module instantiate (modx, mody);
  reg [31:0] a; //reg or wire depending on how it is driven
  reg [31:0] b;
  reg [31:0] c;
  reg [31:0] d;

  wire [31:0] sum1; //wire or logic as driven from an output port
  wire [31:0] sum2;

  add add_0(
    .i( a    ),
    .j( b    ),
    .y( sum1 )
  );

  add add_1(
    .i( c    ),
    .j( d    ),
    .y( sum2 )
  );

endmodule