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64-bit OS refers to the bit width of the general purpose registers. It's able to process 64 bits (data + operations) at a time.

We know that in order for the 64-bit system to be truly useful, programmers need to write 64-bit applications.

However, I wonder what the difference is between a 32-bit application and a 64-bit application? I'm not asking what configuration changes I need to make to compile a 64-bit application; instead, I'd like to know the structural differences of the two applications in memory.

For example, a C program on Linux would typically look like this in memory:

  1. text segment
  2. initialized data segment
  3. uninitialized data segment
  4. heap
  5. stack

I'd imagine the 64-bit application would look the same in terms of layout structure in memory, except that the address for each byte (assuming byte addressable system) has more bits. If that's true, what does the 64-bit imply? simply larger addressable memory space?

Also, when a 64-bit application is compiled, let's assume one instruction in the source code is compiled into the add MIPS instruction in assembly code:

add $1 $2 $1 // $1 += $2;

Each MIPS instruction is encoded in exactly 32 bits. So here's the question, if an application is configured to be compiled as a 64-bit app, what would the add instruction look like? does it still have 32 bits or is it extended to 64 bit which breaks the MIPS rule? If it's still 32 bits, I don't see what difference a 64-bit app make so that it "brings 64 bit OS into full play".

Please enlighten me.

phuclv
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h9uest
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1 Answers1

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First, you tagged the question with MIPS but the ask a general question. The layout of 64-bit apps in MIPS aren't like in other 64-bit architectures. But layouts are how things are arranged in memory, not the segments like you said. Those segments are just memory "zones" and almost all architectures have those segments in their executables

64-bit architectures are not simply an "extend range" of addressable memory but also provide a new instruction set. Because some of the old instructions don't work with 64-bit data so they must create new instructions to deal with.

About instructions, MIPS 64-bit still use 32-bit instruction. If it was extend to 64-bit then what would it contain in the added 32 bits while the other 32-bit was already enough (if not somewhat redundant) to represent all the arguments. But of course there were many new instructions for 64-bit numbers (such as shifting more than 31 or load/store double word...). And btw, the instruction is not correct without ,

phuclv
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  • Thanks for your reply. So, assuming we compile our code with 64bit flags, does it imply that in the text segment of the binary file, it looks like something below: [instruction 1, 64bits][instruction 2, 64bits]... and the cpu just takes 64bits(1 instruction) a time, repeating interpreting the instructions? – h9uest Dec 19 '13 at 15:49
  • No. As I said, the instruction length is still 32 bit. No current architecture uses 64-bit instruction since it's just a waste of instruction cache. With instruction that long you can encode 7 bits of opcode and still have room for encoding 512k registers – phuclv Dec 20 '13 at 00:25
  • OK. So in addition to the larger addressable memory space, the advantage of 64 bit ISA is, we can grab 2 instructions at a time and therefore speed up processing(simplest case, don't consider instruction dependency)? – h9uest Dec 20 '13 at 10:33
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    No. Register width and memory bandwidth doesn't relate to each other. For example the Intel 8088 is a 16-bit CPU but have only 8-bit data bus while modern x86 CPUs may have 64 bits per channel. For models that use quad-channel memory then the bandwidth is 256 bit although the CPU is 32/64-bit. Memories are much slower than cache so high performance CPUs will prefetch the whole block of data into cache instead of fetching only the native word size at a time – phuclv Dec 20 '13 at 13:17
  • In addition, like ARM thumb/thumb2, MIPS also have a compressed 16-bit instruction set (MIPS16e) so just a memory transfer can load much more instructions – phuclv Dec 20 '13 at 13:20
  • I was talking about cpu loading 2 instructions at a time into gpr from instruction cache instead of loading one at a time in the 32 bit case. – h9uest Dec 20 '13 at 17:01
  • The instructions aren't loaded into GPR at any time. Did you see a register for storing instruction in the register set? They're decoded by the decoder and stored seperately. The decoder may also decode many instructions at the same time to adapt superscalar processing – phuclv Dec 21 '13 at 01:18
  • Thank you. I feel like doing some more reading on computer organization. Excuse my ignorance. – h9uest Dec 24 '13 at 11:02