VHDL invert if to reduce nesting

Question

For C#, JetBrains ReSharper often suggests that you invert your if statements to reduce the number of nested if-statements.

For example, it suggests that the code below:

private void Foo()
{
    if (someCondition)
    {
        // Some action
    }
}

could be converted to:

private void Foo()
{
    if (!someCondition) return;
    // Some action
}

Is there a similar way to do this with VHDL code? Even if it is possible, is there a good reason to avoid this coding style in VHDL?

I am wondering if it possible to achieve something like this in VHDL

process(clock)
begin
    if (rising_edge(clock)) then
        -- Some action
    end if;
end process;

becomes

process(clock)
begin
    if (not rising_edge(clock)) then
        return;
    end if;

    -- Some action
end process;

You don't need extra parenthesis in `if` statements in VHDL. You can turn `if (not rising_edge(clock)) then` into the more readable `if not rising_edge(clock) then`. — wjl, Mar 14 '14 at 20:36

score 1 · Answer 1 · answered Mar 14 '14 at 20:52

Naturally there is no early return from a VHDL process because you don't return from a process...

In addition to early return from a subprogram (procedure or function) there are similar approaches to help structure loops : exit (terminating the loop) and next (terminating the current iteration).

These can be embedded in if statements as in your example but there's a more convenient and readable form :

loop
   ...
   exit when A = '1';
   ...
   next when B = '1';
   ...
end loop;

score 1 · Answer 2 · answered Mar 17 '14 at 22:03

Don't.

not rising_edge(clock) is not guaranteed to be synthesizable by the IEEE standard for synthesizable logic. If you know of any tools that do synthesize this, I would be interested to know.

Also, you won't gain anything because (as stated by other repliers) the return statement is not valid in a process.

Try it: Even though this particular style won't work, it was a fair suggestion. If you want to learn about out non-traditional ways of writing code the best way is to write it, simulate it and synthesize it. By experimenting, you will learn a lot and end up to be the smartest designer on your team.

score 0 · Accepted Answer · answered Mar 14 '14 at 19:57

The strategy you suggest is called early return because you are returning from a function early, before reaching its end. It can be done in VHDL and it is as useful as in other languages, but the downside is that it can only be used in subprograms. You cannot "return" from a process.

In theory, you could move the code from inside your process to a procedure, but it would not help achieve what you want. I suggest that you read section 6.3 - Concurrent Procedure Call Statements from Ashenden's Designer's Guide to VHDL to understand the details. In short, there are many restrictions to how the wait statement can be used in a procedure.

score 0 · Answer 4 · answered Mar 17 '14 at 15:22

What's the point? (Does Resharper describe why you want to do this?)

My thoughts on doing this in VHDL-land:

In synthesisable code, it is very likely that - whatever shenanigans you pull to "optimise" your logic - if it turns out to be the same function, the synthesiser will (almost) always (in my experience) find the logic equivalency that mean it ends up with the same optimal logic for the same function as when you write it the straightforward way. (Counter-examples welcome!)

In tetsbench code, I guess you might be able to same some cycles?

From a code-readability perspective: there might be a gain, but if you have that many nested ifs maybe your overall structure needs a re-think...

Resharper makes the suggestion to improve readability. It was discussed in this [StackOverflow question](http://stackoverflow.com/questions/268132/invert-if-statement-to-reduce-nesting) — Scott Lawson, Mar 17 '14 at 23:21

VHDL invert if to reduce nesting

4 Answers4