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I have an error with my code . I've got a given 32b input and an 6b output which should be incremented everytime when the input has 3b of 1 consecutively . For example if the input is 000...111 the output should be 000001.

I tried this code : 

input [31:0] in,
output reg [5:0] out,
input clock

assign n=0;
always @ (posedge clock) begin
**out <= in[n]?in[n+1]?in[n+2]? out+1 : out;**
n++;
end

with no success . Any ideas ?

tshepang
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user3507563
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  • This does not even appear to be syntactically correct verilog. Try using some parentheses. If you want help here you need to make some effort yourself. –  Apr 18 '14 at 14:39
  • out <= (in[n] && in[n+1] && in[n+2])? out+1 : out; – Will Apr 18 '14 at 14:41
  • but using n like that probably will not synthesise – Will Apr 18 '14 at 14:42
  • I'll give you a hint. Create a separate combinational logic block with a for loop that well tell you when to increment. – Greg Apr 18 '14 at 16:15

1 Answers1

1

This can be solved using the elegant solution posted here:

if  (in & (in >>1) & (in>>2)  != '0 )
 out <= out+1;

Basically, if the the bitwise AND of the number with itself shifted 1 bit to the right for three times is non-zero, you increment.

Community
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Ari
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