How to allow two processes to change the value of the same signal

Question

I have two processes that use a signal to synchronize between them, the signal is used is the fallowing way:

type state_machine_1 is
    (st1_state_idle, st1_state_1, st1_state_2, st1_state_3,
     st1_state_4,st1_state_5,st1_state_6);
type state_machine_2 is
    (st2_state_idle, st2_state_1, st2_state_2);

--...

signal st1      : state_machine_1;
signal st2      : state_machine_2;
signal sync_sig : std_logic;

--...

st1_proc: process (CLK, RESET)
begin
    if (RESET = '1') then
        st1                                 <=  st1_state_idle;
        sync_sig                            <=  '0';
    elsif rising_edge(CLK) then
        case st1 is
            when st1_state_idle =>
                --...
                sync_data_is_ready_for_cau  <=  '0';
                if (START = '1') then
                    st1             <= st_state_1;
                else
                    st1             <= st1_state_idle;
                end if;
            ----------------
            when st_state_1 =>
                --...
                st1                 <=  st_state_2;
            ----------------
            when st_state_2 =>
                --...
                st1                 <=  st_state_3;
            ----------------
            when st_state_3 =>
                --...
                if (sync_sig = '0') then
                    st1             <=  st_state_5;
                else
                    st1             <=  st_state_4;
                end if;
            ----------------
            when 4  =>
                if (sync_sig = '0') then
                    st1             <=  st_state_5;
                else
                    st1             <=  st_state_4;
                end if;
            ----------------
            when st_state_5 =>
                --...
                sync_sig    <=  '1';
                st1             <=  st_state_1;
        end case;
    end if;
end process;

st2_proc: process (CLK, RESET, reset_for_st2)
begin
    if (RESET = '1' or reset_for_st2 = '1') then
        st2                 <= st2_state_idle;
    elsif (rising_edge(CLK)) then
        case st2 is
            when st2_state_idle =>
                if (sync_sig = '1') then
                    st2     <=  st2_state_1;
                else
                    st2     <=  st2_state_idle;
                end if;
            ----------------
            when st2_state_1 =>
                --...
                st2     <=  st2_state_2;
            ----------------
            when st_state_2 =>
                --...
                st2           <= st2_state_3;
            ----------------
            when st2_state_3 =>
                --...
                sync_sig  <= '0';
                st2           <= st2_state_idle;
            ----------------
        end case;
    end if;
end process;

All the --... is logic that doesn't touch the synchronization signal, not the states signals (There are some instances where there is an if that waits for a certain signal to advance the states). So there can't be any collision between the values that are put into the synchronization signal, yet, the simulation (Altera Model-Sim) give the signal a U value. How can I use a signal to synchronize between the processes?

Answer 1

'U' (uninitialized) should only be present if you don't have reset active at the start of the simulation. You should actually be getting 'X' when the two FSMs conflict since you have multiple drivers on the sync_sig. This is normal and expected behavior when you have multiple drivers on a resolved type.

It looks like you want each FSM to toggle the state of sync_sig between '1' and '0'. This can be accomplished by describing a JK flip-flop in a separate process with the set and clear signals driven by each FSM on their own. Doing that will eliminate the multiple drivers and allow the FSMs to interoperate.

To save yourself from this problem in the future consider using the unresolved std_ulogic and std_ulogic_vector instead. You will get a compiler error if you mistakenly describe multiple drivers. Resolved types are really only well suited for behavioral simulation and managing bidirectional IOs. They should have never been the "default" for the entirety of a design's signals.