issue with vhdl structural coding

Question

The code below is a simple vhdl structural architecture, however, the concurrent assignment to the signal, comb1, is upsetting the simulation with the outputs (tb_lfsr_out) and comb1 becoming undefined. Please, please help, thank you, Louise.

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity testbench is
end testbench;

architecture behavioural of testbench is

CONSTANT clock_frequency : REAL := 1.0e9;
CONSTANT clock_period : REAL := (1.0/clock_frequency)/2.0;

signal tb_master_clk, comb1: STD_LOGIC := '0';

signal tb_lfsr_out : std_logic_vector(2 DOWNTO 0) := "111";

component dff
port
  (
    q: out STD_LOGIC;
    d, clk: in STD_LOGIC
  );
end component;

begin

-- Clock/Start Conversion Generator
tb_master_clk <= (NOT tb_master_clk) AFTER (1 SEC * clock_period);

comb1 <= tb_lfsr_out(0) xor tb_lfsr_out(2);

dff6: dff port map (tb_lfsr_out(2), tb_lfsr_out(1), tb_master_clk);
dff7: dff port map (tb_lfsr_out(1), tb_lfsr_out(0), tb_master_clk);
dff8: dff port map (tb_lfsr_out(0), comb1, tb_master_clk);

end behavioural;

Answer 1

It's just a little more complex than Radix Ciano(1) says. All tb_lfsr_out elements are showing 'U' from Now = 0 ns. The reason why is that all of the D flip flops aren't initialized.

All tb_lfsr_out elements are showing 'U' from Now = 0 ns. The reason why is that all of the D flip flops aren't initialized.

If you reset all the flip flops the result will always be '0' without a '1' to cause a flip in the XOR gate.

Preset the D flip flops (which can come for free in an FPGA implementation):

This was done by simply adding a default value:

q:      out std_logic := '1';

---

(1) Yes it's a minor change, and to all appearances someone changed their user name and if asked I would have changed Radix to Ciano. Making changes simply to cross a threshold is ridiculous.

The entire purpose of this answer was to avoid stepping on the other answerer's rights of authorship and now he's done the very thing. The issue with his answer being that the complimentary property of XOR prevented the LFSR from working when all inputs were '0's or any inputs were metavalues.

And while you're at it no one noticed the error in the waveform now corrected, apparently too self absorbed in playing games with answer edits. (The signals after the label dff8 were actually from dff7).

There's a message here which is in the form of a question. What's the purpose in answering questions on stackoverflow? See Why I no longer contribute to StackOverflow . And note Mr. Richter's reputation has continued to eek upward, including for the example post on goto he cites as likely to induce severe ire. (And the message there is have patience all you petty editors, sooner or later you're 'reputation' will reach self sustaining levels unless the system is altered to prevent it).

Also note the question's author has to date and after an impassioned plea closing his question not show acceptance of nor use for any answer.

In the mean time quit spoiling why I answer questions on VHDL by changing the words I write, although I have to admit the edit voting history was entertaining.