Variable and constants in VHDL

Question

Where the KEYWORDS variable and constant have to be used in VHDL coding, I'm aware of the scope of both of them, but unable to figure out which one has to be used when??

Answer 1

Use Variable when you want to vary (modify) the quantity you are declaring, Constant when you don't. Or Signal if you want to vary it AND it's shared between different processes, ports or components.

But remember that Signal has different update semantics, avoiding the hazards and errors that can occur if you shared variables between processes in any language.

Answer 2

Brian is correct. Only use variables for data that changes. Constants (as their name implies) is for data that does not change. In general I don't recommend that beginners to VHDL use variables, as they can synthesize differently than expected. I would recommend sticking to signals for holding your dynamic data.

Variables update immediately when they are assigned. Signals take one clock cycle if they are in a sequential process or update immediately if they are in a combinational piece of code

Read more about variables vs. signals in VHDL