linking output from module 2 to if else statement of module 1 VERILOG

Question

My objective is when my input "start=1" the shifting is endless, and when I change it to "start=0" the shifting stops.

At that point when my output (result1 = 1) and (result = 5) it should end at the $finish command line. but instead it ends in the $stop in the testbench.

I think the problem is that the two output (result1 and result2) in the 2nd module is not linked in the 1st module.

How can I link the output in the 2nd module to the 1st module so that the condition in my if-else statement in the 1st module is satisfied and will proceed to $finish.

I preset my testbench code so that when start = 0; it stops at result1 = 1 and result2 = 5.

here is my code //1st module

module random(ps_in, ps_out, clk, start, result1, result2);

input      ps_in;
output reg ps_out;
input      clk;
input      start;

output [2:0] result1; //1st output based on the 2nd module
output [2:0] result2; //2nd output based on the 2nd module

reg count;

initial begin
  ps_out = 0;
  count  = 0;
end

always @ (posedge clk)
  if (start!=0) begin
    ps_out = ps_in;
  end
  else if (start!=1 && count!=1) begin
    ps_out = ps_in;
    count  = count + 1;
  end
  else if (start!=1 && result1==3'b001 && result2==3'b101) begin
    $finish; //IT MUST END IN THIS LINE
  end

endmodule



//2nd module


module smachine (start,clk,result1,result2);

input start;
input clk;

output [2:0] result1;
output [2:0] result2;

wire feedback1, feedback2, ffq1, ffq2, ffq3, ffq4;

random r1 (feedback1,  ffq1,          clk, start);
random r2 (ffq1,          result1[2], clk, start);
random r3 (result1[2], result1[1], clk, start);
random r4 (result1[1], result1[0], clk, start);
random r5 (result1[0], ffq2,       clk, start);

assign feedback1 = (result1[1] ^~ffq2);

random r6 (feedback2,  result2[2], clk, start);
random r7 (result2[2], result2[1], clk, start);
random r8 (result2[1], ffq3,       clk, start);
random r9 (ffq3,          result2[0], clk, start);
random r10(result2[0], ffq4,       clk, start);

assign feedback2 = (ffq3 ^~ffq4);

endmodule

here is my testbench

module qqqq;

    // Inputs
    reg start;
    reg clk;

    // Outputs
    wire [2:0] result1;
    wire [2:0] result2;

    // Instantiate the Unit Under Test (UUT)
    smachine uut (
        .start(start), 
        .clk(clk), 
        .result1(result1), 
        .result2(result2)
    );

always
#5 clk = ~clk;

    initial begin
        // Initialize Inputs
        #10 start = 1;
        clk = 0;
        #50 start = 0;
        clk = 0;
        #50 $stop;
    end

    endmodule

yes its for synthesis.. i was about to put a jackpot indicator when it satisfies the condition but i started it at $finish to test the code.. its like a roulette game. — John Michael, Jul 07 '14 at 11:20
"when input "start=1" the shifting is endless" Where does the shifting happen? The only functional unit is to increment count `count = count + 1;`. — Morgan, Jul 08 '14 at 06:52

score 1 · Answer 1 · edited May 23 '17 at 11:57

1

It may be beneficial to your understanding to read the question on how-to-instantiate-a-module.

In module random result[12] are outputs:

output [2:0] result1; //1st output based on the 2nd module
output [2:0] result2; //2nd output based on the 2nd module

They are never assigned a value therefore the condition result1==3'b001 && result2==3'b101 is never true.

if (start!=1 && result1==3'b001 && result2==3'b101) begin
  $finish; //IT MUST END IN THIS LINE
end

That is why it does not exit on the $finish.

May be they should be inputs? and then you would need to drive values into it from module smachine. currently you only make 4 connections ignoring the last 2 which would be result and result2.

Your Testbench module qqqq; does not instantiate the smachine, should be:

module tb;
  logic clk;
  logic start;
  logic [2:0] result1;
  logic [2:0] result2;

smachine DUT (
  .start (start), //Port connection
  .clk   (clk),   //Driving Signals to smachine instance DUT

  .result1 (result1),
  .result2 (result2)
);  

initial 
  forever
    #5 clk = ~clk;

 initial begin
   // Initialize Inputs
   #10 start = 1;
   clk = 0;
   #50 start = 0;
   clk = 0;
   #50 $stop; // BUT IT ENDS HERE
  end

endmodule

An example of this can be found on EDAplayground.

Adding example requested in comments to capture output to different location, this will iterate over 4 outputs.

reg [1:0] state = 2'b0; //state is a basic sounter

//Nextstate assignment
always @(posedge clk) begin
  state <= nextstate ;
end

//Next state logic
always @* begin //Combinatorial section
  nextstate = state+1 ;
end

// State Output
always @( posedge clk) begin
  case(state)
    2'd0 : output1 <= ps_out;
    2'd1 : output2 <= ps_out;
    2'd2 : output3 <= ps_out;
    2'd3 : output4 <= ps_out;
end

edited May 23 '17 at 11:57

Community

1
1

answered Jul 07 '14 at 12:34

Morgan

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i was assuming that the results[12] in the random module is linked to the results[12] in smachine module.. my testbench is linked to module smachine because that module is doing the shifting (random) process.. any advice that i could use to link the results[12] from the smachine module to the results[12] in the random module?? thanks – John Michael Jul 07 '14 at 13:00
@JohnMichael you keep saying linking, but that is not very clear to me. One of the modules must create the value. If a sub module receives it make an input and connect the port. if the sub module creates it drive the value out of the port and connect it. You have unconnected ports mentioned in last paragraph of answer. – Morgan Jul 07 '14 at 13:29
@JohnMichael There is no auto linking, Any module not instantiated becomes a top level module. Your tb should really instantiate the module smachine and you connect the ports correctly. – Morgan Jul 07 '14 at 13:36
is there a way to instantiate the two modules? – John Michael Jul 08 '14 at 00:06
i apologize for my ignorance.. im just new in verilog coding so im trying to understand it one by one – John Michael Jul 08 '14 at 00:22
i have a perfect idea on how to have an output of results[12] in module random the same as the output results[12] in module smachine.. is there a way to change the output destination of each ps_out in every clock pulse.. lets say @ clock 1: output1 = ps_out; @ clock 2: output2 = ps_out; @ clock 3: output3 = ps_out; and so on?? – John Michael Jul 08 '14 at 00:48
@JohnMichael in smachine r1 to r10 are your module random instances. you just need to instance smachine in your testbench. – Morgan Jul 08 '14 at 05:10
@JohnMichael I have added an example for capturing results to different locations. For instanciating modules [see here](http://stackoverflow.com/q/20066850/97073) – Morgan Jul 08 '14 at 06:47
thank you mr. morgan for your attached information.. i was able to finish my work.. thank you again so much! :D – John Michael Jul 13 '14 at 07:13
@JohnMichael if the answer was correct could you accept it. Verilog can be quite difficult to learn, its not like programming in other languages, try yo have fun learning. – Morgan Jul 13 '14 at 07:41

linking output from module 2 to if else statement of module 1 VERILOG

1 Answers1