Bad coding style for a follower flip flop

Question

The following is a code to capture data and the captured data is passed through a follower flip flop. The author of Paper on Synchronous and Asynchronous Resets says that the the rst_n will be used as data enable for the second flip-flop, because both flip-flops are inferred from the same procedural block. Can anyone explain how will the simulator interpret this to be a Load-data signal only for the second flip flop?

module badFFstyle (
 output reg q2,
 input d, clk, rst_n
);

  reg q1;

  always @(posedge clk)
    if (!rst_n) q1 <= 1'b0;
    else begin
      q1 <= d;
      q2 <= q1;
    end
endmodule

See [this answer](http://stackoverflow.com/a/21477457/579887) for logic diagrams and a solution to mixing registers that are reset with registers that aren't into a single `always` block. — Chiggs, Sep 17 '14 at 09:24
It makes more sense when it is labeled as enable signal rather than "load-data" used in paper. Thank You — chitranna, Sep 21 '14 at 12:17

score 0 · Accepted Answer · edited Sep 17 '14 at 15:29

The rst_n signal will be used as input data (along with input d) for q1 output and as a clock enable for q2 output. In order to understand the difference, you need to think when should the flip-flop sample it's input:

q1 will sample its input every clock cycle, when the input is rst_n & d.
q2 will sample its input only on clock cycles that occurs when rst_n = 1 when the input is q1.

Meaning, that when rst_n = 0, the second flip-flop will hold to its value regardless to d and 1q1`.

Bad coding style for a follower flip flop

1 Answers1