Getting strange error in verilog (vcs) when trying to use if/else blocks

Question

I am trying to write an "inverter" function for a 2's compliment adder. My instructor wants me to use if/else statements in order to implement it. The module is supposed to take an 8 bit number and flip the bits (so zero to ones/ones to zeros). I wrote this module:

    module inverter(b, bnot);
    input [7:0] b;
    output [7:0]bnot;

    if (b[0] == 0) begin
    assign bnot[0] = 1;
    end else begin
    assign bnot[0] = 0;
    end

    //repeat for bits 1-7

When I try and compile and compile it using this command I got the following errors:

    vcs +v2k inverter.v
    Error-[V2005S] Verilog 2005 IEEE 1364-2005 syntax used.
    inverter.v, 16
    Please compile with -sverilog or -v2005 to support this construct: generate
   blocks without generate/endgenerate keywords.

So I added the -v2005 argument and then I get this error:

  vcs +v2k -v2005 inverter.v
 Elaboration time unknown or bad value encountered for generate if-statement
 condition expression.
 Please make sure it is elaboration time constant.

Someone mind explaining to me what I am doing wrong? Very new to all of this, and very confused :). Thanks!

score 5 · Answer 1 · edited May 23 '17 at 10:24

assign statements like this declare combinatorial hardware which drive the assigned wire. Since you have put if/else around it it looks like you are generating hardware on the fly as required, which you can not do. Generate statements are away of paramertising code with variable instance based on constant parameters which is why in this situation you get that quite confusing error.

Two solutions:

Use a ternary operator to select the value.

assign bnot[0] = b[0] ? 1'b0 : 1'b1;

Which is the same as assign bnot[0] = ~b[0].

Or use a combinatorial always block, output must be declared as reg.

module inverter(
  input      [7:0] b,
  output reg [7:0] bnot
);
always @* begin
  if (b[0] == 0) begin
    bnot[0] = 1;
  end else begin
    bnot[0] = 0;
  end
end

Note in the above example the output is declared as reg not wire, we wrap code with an always @* and we do not use assign keyword.

Verliog reg vs wire is a simulator optimisation and you just need to use the correct one, further answers which elaborate on this are Verilog Input Output types, SystemVerilog datatypes.

Getting strange error in verilog (vcs) when trying to use if/else blocks

1 Answers1