Is there a system task or pre-processor directive in SystemVerilog for retrieving the used standard version?

Question

I implemented a SV module which contains soft constraints. However, as far as I know soft constraints are only supported since 1800-2012 standard. Therefore I would like to add an alternative implementation in case a simulator is used that only supports older standard versions.
Is there a way to retrieve this information with a system task or pre-processor directive in such a way:

if($get_version_specifier == "1800-2012")
   // do fancy stuff with soft constraints
else
   // alternative fancy stuff

I already found an option for a similar problem by using begin_keywords, end_keywords, but I think that would not solve my issue since it only defines the set of keywords for a specific standard. And if the simulator does not support this version I guess only an error would occur.

Thanks in advance!
sebs

score 2 · Accepted Answer · answered Oct 23 '14 at 18:11

The problem you ask about is more complicated than it seems. Different features of SystemVerilog are implemented by different versions of tool; sometimes before the standard is released, sometimes after. I do know that some tools supported soft constraints before the release of the 1800-2012 standard, and no commercial tool that I know of has yet to support operator overloading, which was in the first IEEE 1800-2005 standard.

A better solution would be to define a set of macros like USE_SOFT_CONSTRAINTS for features that do not have universal support. Then you can include a common featureset.svh file that defines the feature set you want to use. Another good practice is to DOCUMENT the reason you added a specific feature macro (i.e the tool version you were using that didn't support the feature and why you decided it was worth the effort to implement both branches of the code).

score 0 · Answer 2 · edited May 23 '17 at 12:05

As far as I know, there isn't any "standard" way of getting the version of the standard you are using. C++ had a similar problem before the 2011 release (see here). One answer there states that different compilers added different proprietary defines (something like the INCA macro set for the Incisive simulator). You'll have to ask your simulator vendor if a define for the version of the SV standard exists (something like SV2012_OR_GREATER).

Cadence, for example, has something like this for Specman, so if they're consistent they might have this for SystemVerilog as well. Assuming such a thing exists, you could have:

`ifdef SV_2012_OR_GREATER
  // do fancy stuff with soft constraints
`else
  // alternative fancy stuff
`endif

Bonus: Soft constraints are a declarative construct, so I don't see how you could use an if block to decide whether to use them or not (unless maybe if it's an if inside a constraint block). Also, I'm not sure whether you're able to truly emulate soft constraints in any way, however fancy your approach is, so I don't know if it really makes sense to try.

You probably could emulate a soft constraint by calling randomize(), and checking the result. If it returns 0 (i.e. it has failed to randomize), then you turn off your "soft constraint" and call randomize() again. — Stan, Oct 26 '14 at 01:49
@stan Yeah, but how do you know if the randomize failed because that constraint and not another? — Tudor Timi, Oct 26 '14 at 09:21
The setup will break if your randomizations can fail for other reasons, for sure. But in most cases, you don't expect the randomization to fail unless something went wrong. — Stan, Oct 26 '14 at 14:50

Is there a system task or pre-processor directive in SystemVerilog for retrieving the used standard version?

2 Answers2