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I have been studying how a computer works internally. So far so good.

However I am a bit stuck with pipelining. Tough I can understand (roughly) what it is and how it works, when trying to do some exercises I find myself cornered with terms I cannot find anywhere clear enough for a beginner.

Thus, I wonder if somebody here knows any kind of academic resource so that I can keep on with studies.

Right now I am doing an exercise with this, I have searched quite a lot believe me, but cannot find anything clarifying.

Assume we use a pipeline with a 5 stage instruction: IF, ID, EX, MEM and WR. Consider the following sequence of instructions:

ADD $r0, $r1, $r2

SUB $r4, $r0, $r3

AND $r5, $r0, $r6

OR  $r7, $r0, $r8

XOR $r9, $r0, $r10

I am not asking for anybody to explain it line by line, just some online resources I am obviously missing...

Thanks!

EDIT: I have found some quite nice information about MIPS implementation of Pipelining. Here Link http://www.ece.lsu.edu/ee4720/2010f/lsli06.pdf and here http://www.mrc.uidaho.edu/mrc/people/jff/digital/MIPSir.html

eneko
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    Asking for links to offsite resources is off-topic hereabouts. – High Performance Mark Jan 05 '15 at 17:01
  • This is offtopic for the site, but here's the gist: If this is a MIPS CPU's instruction set, then line 1 adds `r1` and `r2` and discards the result by writing it to `r0`, which is a register that can only be read as zero and to which writes are ignored. Line 2 computes `0-r3`, effectively negating `r3`, and saves it to `r4`. Line 3 zeroes `r5`, because anything AND 0 is 0. Line 4 copies `r8` to `r7`, since anything OR 0 is unaltered. Line 5 copies `r10` to `r9`, since anything XOR 0 is unaltered. – Iwillnotexist Idonotexist Jan 05 '15 at 17:08
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    it has nothing to do with pipelining i am afraid. pipelining is related to intra-instruction level thing, and your code says nothing about this. – Jason Hu Jan 05 '15 at 17:12

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