I am wondering how the os decides between write back and write through attributes for a page in the MMU page table in Arm v7 and armv8. Thanks
1 Answers
First you might want to understand what each is. Ref1 Ref2
- Write through - data written to RAM immediately.
- Write back - data written on eviction.
It is easier to make a write through cache (in hardware) than a write back. For this reason, some older ARM CPUs may have a hard coded write through only cache. ARMv4/5 have this as an option. By the time ARMv7/8 are around the logic for the write back is very small compared to other logic, so the CPU/MMU support both.
There are also some kernel command line options such as cachepolicy, nocache and nowb in mmu.c; these only apply to early boot and are mainly for older ARM CPUs, but you could still use them for ARMv7/8.
Generally, WRITEBACK is highly valuable as most systems have SDRAM which gives a bonus for writing multiple entries at one time. Often code performs read-modify-write cycles; perhaps multiple times on the same memory or structure. A typical cache line corresponds well to an SDRAM burst length (no coincidence).
There are some cases such as an LCD with DMA where you may wish to use WRITETHROUGH, so typically these options are chosen by a kernel allocator. It will choose the correct property to the non-architecture API.
User space would always want and get WRITEBACK memory. It maybe possible that some mmap
LCD frame buffer is WRITETHROUGH, but it is more possible that it is un-cached.
I am wondering how the os [linux] decides between write back and write through attributes for a page in the MMU page table in Arm v7 and armv8.
The decision depends on the use of the memory. Most frequently the WRITEBACK mode will be used in user-space except for some rare instances where a drivers memory might be exposed. Ie, for memory that is only used by CPUs in the system, WRITEBACK is always best. It is only when there is something else looking at the memory (like an LCD DMA) where the WRITETHROUGH will be better. For the LCD DMA, you want the stuff you write to memory to be displayed on screen immediately.

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Oddly enough, writes to SDRAM are often faster than reads (for the CPU). If the entire cache is *write through*, then a cache line is never *dirty* and the cache is much simpler. So at some point people did make ARM hardware that only supported one mode. – artless noise Jan 12 '15 at 20:46
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I am not an expert in ARM64 by any means. However, the [arm64 mmu.c](https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/mm/mmu.c) seems to follow the plain ARM version; your ARMv8 can be used in both modes. – artless noise Jan 12 '15 at 20:52