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In AT&T syntax instructions often have to be suffixed with the appropriate operand size, with q for operations on 64-bit operands. However in MMX and SSE there is also movq instruction, with the q being in the original Intel mnemonic and not an additional suffix.

So how will this be represented in AT&T? Is another q suffix needed like

movqq %mm1, %mm0
movqq %xmm1, %xmm0

or not?

And if there are any other instructions that end like AT&T suffixes (like paddd, slld), do they work the same way?

Peter Cordes
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phuclv
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2 Answers2

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AT&T syntax basically doesn't do anything about conflicts between mnemonic+suffix vs. other mnemonics. Register operands always disambiguate between a mov mnemonic with a q operand-size suffix vs. the movq mnemonic

movq %xmm0, %xmm0, movq %rax, %xmm0, and movq %xmm0, %rax are 3 different opcodes that all use the same mnemonic (movq in both Intel and AT&T syntax).

A suffix is not allowed on the movq mnemonic: Error: invalid instruction suffix for 'movq'. This is normal because there's no possible ambiguity with respect to operand-size. movq always moves 64 bits, so a q suffix would be redundant.

Does this make parsing AT&T harder than parsing Intel syntax? Well before MMX even existed (thus also before x86-64), movl was still the mnemonic for 6 different opcodes (Intel's insn set ref manual entry for mov lists them all, with their numeric opcode):

  • MOV r/m32,r32
  • MOV r32,r/m32 (assembler can choose either opcode if both operands are regs)
  • MOV r32, imm32 (short form)
  • MOV r/m32, imm32 (with a modr/m, usable for memory operands).
  • also MOV moffs32,EAX and MOV EAX,moffs32, as an optimization (no ModR/M) for storing/loading with a 32-bit absolute address.

And that's not counting mov to/from segment, control, and debug registers. Just like with movq %xmm0, %rax, AT&T syntax has always had to deal with mov %ds, %ax.

Adding a few more forms with different registers to disambiguate is probably not much harder to parse.

Besides that, operand-size suffixes are optional when registers determine the operand-size anyway. mov %rax, %rcx is legal, and a suffix is only needed for moving an immediate to memory. mov $1, (%rsi) is illegal because neither operand implies an operand-size, and there's no suffix to make it explicit.

Peter Cordes
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movq was introduced with MMX to facilitate movement of quadwords between MMX registers and non-MMX registers. It's a general-purpose opcode; you can move a quadword between an mmx register and any other register (mmx or non-mmx), or even between non-mmx registers.

In other words, there aren't two different opcodes. Consequently, the syntax is always movq.

Robert Harvey
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  • but in Intel syntax there are 2 different mnemomics: `movq`/`movd` for MMX and `mov` for normal registers – phuclv Jan 16 '15 at 18:29
  • Even for quadwords? Try `movq` for two ordinary registers; if that doesn't work, then report back here, and I'll see what I can do. – Robert Harvey Jan 16 '15 at 18:30
  • Yes. You use `mov rax, rbx`, not `movq rax, rbx` even when they are quadwords – phuclv Jan 16 '15 at 18:31
  • Then limit your use of `movq` to quadword moves that only involve mmx registers. `movq` is the name of an opcode; there's no expectation (at least on my part) that the `q` has any special meaning other than it is a letter in the opcode. – Robert Harvey Jan 16 '15 at 18:31
  • Try `movq` on two non-mmx registers; I suspect it will still work. – Robert Harvey Jan 16 '15 at 18:34
  • It doesn't work in Intel syntax but will work in AT&T if the regisers are 64 bits. It's just "counterintuitive" to me in this case when AT&T uses only 1 mnemonic for many cases when it's usually more "complicated" than Intel and uses separate mnemonics for different instructions – phuclv Jan 16 '15 at 18:43
  • Why would you have the expectation that two completely different assemblers would behave exactly the same way? Perhaps its counter-intuitive, but it sounds like it is what it is. – Robert Harvey Jan 16 '15 at 18:45