VHDL - Shift operation of N times with concatenation

Question

I would like to know how can I do a shift operation in VHDL if I have 2 inputs, one input, DATA1 is a number (std_logic_vector), and the second input DATA2 represents the number of times I want to shift the first input. For example, if I must shift left always only one time, the code is

OUTALU <= '0' & DATA1(N-1 downto 1);

If I would like to shift DATA2 times, is it right writing:

for i in 0 to DATA2 loop
  OUTALU <= '0' & DATA1(N-1 downto 1);
  DATA1 <= OUTALU
end loop;

is it right? I must define signals and assign to these signals DATA1 and DATA2? Thank you for help

take a look at : http://stackoverflow.com/questions/9018087/shift-a-std-logic-vector-of-n-bit-to-right-or-left — Nicolas Roudel, Apr 01 '15 at 09:22

Jonathan Drolet · Accepted Answer · 2015-04-01T03:37:20.970

2

What you seek is a barrel-shifter. You can do that like this:

OUTALU <= std_logic_vector(shift_left(unsigned(DATA1),  to_integer(unsigned(DATA2)))); -- Shift left
OUTALU <= std_logic_vector(shift_left(unsigned(DATA1),  to_integer(unsigned(DATA2)))); -- Shift right
OUTALU <= std_logic_vector(shift_left(  signed(DATA1),  to_integer(unsigned(DATA2)))); -- Arithmetic shift left
OUTALU <= std_logic_vector(shift_left(  signed(DATA1),  to_integer(unsigned(DATA2)))); -- Arithmetic shift right

This implies you use ieee.numeric_std.all' and thatDATA1andDATA2` are std_logic_vector, thus the casts.

edited Apr 01 '15 at 03:37

answered Apr 01 '15 at 03:30

Jonathan Drolet

3,318
1
12
23

shift_left is already implement function? Is a logical or arithmetic shift? – Develobeer Apr 01 '15 at 09:10
1

It is implemented in numeric_std. If the input is `unsigned`, it is a logical shift. On the other hand, it performs arithmetic shift when the inout is `signed`. – Jonathan Drolet Apr 01 '15 at 14:34

score 0 · Answer 2 · answered Apr 01 '15 at 09:35

0

datao <= std_logic_vector(unsigned(data1) sll to_integer(unsigned(data2)));

sll is shift left logical, filled with ‘0’

you can also use sla (shift left arithmetic, filled with right bit) instead sll.

ps: datao <= '0' & data1(7 downto 1) is a right shifter, not left :). use srl or sra.

answered Apr 01 '15 at 09:35

Nicolas Roudel

91
6

The use of sll, sla, and cie is discouraged in favor of shift_left/shift_right. The operators were not defined properly and can lead to unexpected behaviour, such as sla will copying the sign bit to the lsb! – Jonathan Drolet Apr 01 '15 at 14:40

VHDL - Shift operation of N times with concatenation

2 Answers2