how to force recompile when changing Makefile flags?

Question

I am compiling some project with dependency so i won't have to recompile each time, but when i am adding -Dsome_flags to my CFLAGS, it is not recompiling.

dep: $(CPPS)
    $(CC) $(CFLAGS) $(INC) -M $(CPPS) > dep

i add to my CFLAS -DDEBUG_FLAG and it forces me to do make clean and make instead of make.

You may not need a dependency generator rule at all. http://stackoverflow.com/a/7358961/412080 — Maxim Egorushkin, Apr 27 '15 at 16:38

score 6 · Answer 1 · answered Apr 26 '15 at 12:31

6

It won't recompile because you don't have the makefile itself listed as a dependency.

dep: $(CPPS) Makefile
    $(CC) $(CFLAGS) $(INC) -M $(CPPS) > dep

That said, if you're feeding in make flags from the command line (e.g. CFLAGS=-O3 make all), make has no way of detecting that you've changed those and forcing a full build.

answered Apr 26 '15 at 12:31

Mike DeSimone

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No way of overcoming the command line issue. `make` has no way to remember how it was last run. Also, you'll have to change `Makefile` to wherever your makefile is. – Mike DeSimone Apr 26 '15 at 17:44
@MikeDeSimone the following question has the same set of issues when dealing with multiple targets and their dependencies? https://stackoverflow.com/questions/30043480/make-recipe-to-prevent-rebuilding-of-non-dependent-targets# – Sami Kenjat May 05 '15 at 05:34
@SamiKenjat That one is trying to prevent unneeded rebuilds. This one is trying to prevent *skipping* a needed rebuild. – Mike DeSimone May 06 '15 at 00:09

score 3 · Accepted Answer · answered Apr 26 '15 at 14:35

3

The simplest, in my opinion, would be to do a make clean and then a make. This is of course assuming that you want all source files to be recompiled due to the change in compiler flags. But you seem to not like this method.

If you want to modify the makefile, you can add the name of your makefile to every rule for compiling source files, for example:

    somefile.o : somefile.cpp <makefile_name>
            $(CC) -c $(CFLAGS) somefile.cpp -o somefile.o

or

    %.o : %.c <makefile_name> 
            $(CC) -c $(CFLAGS) somefile.cpp -o somefile.o

Given the size of the project, and the number of rules involved, doing a make clean; make may be the easiest and fastest method. However, as always, you mileage my vary.

Just my $0.02 worth, hope it helps T.

answered Apr 26 '15 at 14:35

thurizas

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This is pretty much the method I've seen in practice. – Mike DeSimone Apr 26 '15 at 17:44
This doesn't work if the flags changed due to command line changes. For example `make CFLAGS=-DDEBUG` won't recompile anything. – Kevin Cox Jun 16 '17 at 19:34
@KevinCox yea, you are correct. However recall how make works, It compares the last modified time stamp of each target against the last modified time stamp of all of that target dependencies. If one of the dependencies have been modified after that target was last built, then the target is rebuilt. If you modify a flag on the command line like you suggest, then there is not change to the file system and you do not get the desired recompilation. In a case like this, the use of `make clean` `make CFLAGS=-DDEBUG` should do the trick – thurizas Jun 18 '17 at 15:40

score 2 · Answer 3 · answered Apr 27 '15 at 16:34

Makefile looks for changes based on the data it has. Your Makefile states the only dependencies are defined under $(CPPS).

dep: $(CPPS)
    $(CC) $(CFLAGS) $(INC) -M $(CPPS) > dep

So the make tracks the changes only within the given list, i.e., $(CPPS). So the resolution is:

dep: $(CPPS) Makefile
    $(CC) $(CFLAGS) $(INC) -M $(CPPS) > dep

For complete but non-complex example, here is my Makefile for a helloworld program:

OBJS = helloworld.o
default: hw

%.o: %.c Makefile
    gcc -c $< -o $@

hw: $(OBJS)
    gcc $(OBJS) -o $@

clean:
    -rm -f $(OBJS) hw

Everytime I change my makefile it gets recompile! :)

how to force recompile when changing Makefile flags?

3 Answers3

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