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Context:

x86_64, intel core 2 duo.

I searched through the 3 intel doc volumes, and may have missed the right section, hence the question.

A tlb can have up to 4096 entries, that is a lot in my book. But that is not that much in a SMP system after all. Especially if the tlb is not flushed thanks to the tag bit -> almost full all the time.

Imagine the case in which you have your memory properly mapped throughout the 4 page tables. Imagine that you have more than 4096 entries (i know..), and that, obviously, it is too much for the tlb.

I know that x86 doesn't automatically generate page fault on tlb miss.

Question:

Should I be assured that the mmu will walk the page tables and replace one of the entries automatically (since it is already correctly mapped) ?

It would make sense, since there is nothing more to do on the operating system side, the memory is already mapped.

Thanks

Peter Cordes
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Larry
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    It probably uses pLRU bits on the TLB entries https://patents.google.com/patent/US20100306499 – Lewis Kelsey May 04 '21 at 04:12
  • See [What happens after a L2 TLB miss?](https://stackoverflow.com/q/32256250) for details *other* than the eviction mechanism / replacement policy. – Peter Cordes May 04 '21 at 04:45

1 Answers1

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Yes, on a TLB miss the MMU will walk the page table and replace an existing TLB entry if there is no empty space available to hold the new entry.

A TLB miss will only result in a page fault if the page is not present in memory.

Craig S. Anderson
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