The translation lookaside buffer (TLB) enables modern CPUs to quickly map virtual memory addresses to physical memory addresses and vice versa. Operations that flush the TLB cause a performance hit until it is repopulated.
Questions tagged [tlb]
289 questions
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What is TLB shootdown?
What is a TLB shootdown in SMPs?
I am unable to find much information regarding this concept. Any good example would be very much appreciated.
mousey
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cache miss, a TLB miss and page fault
Can someone clearly explain me the difference between a cache miss, a tlb miss and page fault, and how do these affect the effective memory access time?
Pushp Sra
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Difference between logical addresses, and physical addresses?
I am reading Operating Systems Concept and I am on the 8th chapter! However I could use some clarification, or reassurance that my understanding is correct.
Logical Addresses: Logical addresses are generated by the CPU, according to the book. What…
user427390
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Physical or virtual addressing is used in processors x86/x86_64 for caching in the L1, L2 and L3?
Which addressing is used in processors x86/x86_64 for caching in the L1, L2 and L3(LLC) - physical or virtual(using PT/PTE and TLB) and somehow does PAT(page attribute table) affect to it?
And is there difference between the drivers(kernel-space)…
Alex
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What happens after a L2 TLB miss?
I'm struggling to understand what happens when the first two levels of the Translation Lookaside Buffer result in misses?
I am unsure whether "page walking" occurs in special hardware circuitry, or whether the page tables are stored in the L2/L3…
user997112
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Memory barriers and the TLB
Memory barriers guarantee that the data cache will be consistent. However, does it guarantee that the TLB will be consistent?
I am seeing a problem where the JVM (java 7 update 1) sometimes crashes with memory errors (SIGBUS, SIGSEG) when passing a…
Peter Lawrey
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Difference between Cache and Translation LookAside Buffer[TLB]
What is the difference between Cache and Translation LookAside Buffer [TLB] ?
Kaizen
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When to do or not do INVLPG, MOV to CR3 to minimize TLB flushing
Prologue
I am an operating system hobbyist, and my kernel runs on 80486+, and already supports virtual memory.
Starting from 80386, the x86 processor family by Intel and various clones thereof has supported virtual memory with paging. It is well…
Antti Haapala -- Слава Україні
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TLB misses vs cache misses?
Could someone please explain the difference between a TLB (Translation lookaside buffer) miss and a cache miss?
I believe I found out TLB refers to some sort of virtual memory address but I wasn't overly clear what this actually meant?
I understand…
intrigued_66
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How prompt is x86 at setting the page dirty bit?
From a software point of view, what is the latency between an instruction that dirties a memory page and when the core actually marks the page dirty in the Page Table Entry (PTE)?
In other words, if an instruction dirties a page, can the very next…
srking
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calculate the effective access time
This is a paragraph from Operating System Concepts, 9th edition by Silberschatz et al:
The percentage of times that the page number of interest is found in
the TLB is called the hit ratio. An 80-percent hit ratio, for example,
means that we…
Aysha Almaqtari
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In what circumstances can large pages produce a speedup?
Modern x86 CPUs have the ability to support larger page sizes than the legacy 4K (ie 2MB or 4MB), and there are OS facilities (Linux, Windows) to access this functionality.
The Microsoft link above states large pages "increase the efficiency of the…
timday
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Faster way to move memory page than mremap()?
I've been experimenting with mremap(). I'd like to be able to move virtual memory pages around at high speeds. At least higher speeds than copying them. I have some ideas for algorithms which could make use of being able to move memory pages really…
simonhf
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Is the TLB shared between multiple cores?
I've heard that TLB is maintained by the MMU not the CPU cache.
Then Does One TLB exist on the CPU and is shared between all processor or each processor has its own TLB cache?
Could anyone please explain relationship between MMU and L1, L2 Cache?
ruach
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TLB vs Page Table
The page table associate each virtual page with its associated physical frame.
The TLB does the same except it only contains a subset of the page table.
What is the purpose of the TLB if page table does the same thing and has more data?
RainingChain
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