88

What is a TLB shootdown in SMPs?

I am unable to find much information regarding this concept. Any good example would be very much appreciated.

Peter Mortensen
  • 30,738
  • 21
  • 105
  • 131
mousey
  • 11,601
  • 16
  • 52
  • 59
  • 1
    Is this a programming question? – Gabe Sep 20 '10 at 02:45
  • @Gabe, I guess it's a programming question if @mousey is trying to implement a kernel. Some clarification on his part would be much appreciated. – Carl Norum Sep 20 '10 at 02:47
  • 4
    yes I am trying to implement a kernel. – mousey Sep 20 '10 at 02:51
  • 55
    The constant dogmatic attempts to compartmentalize programming away from systems concepts is a fundamental flaw of Stackoverflow. The very name of the site is a systems concept. If you are a systems programmer you cannot separate these concepts from the code that controls them. We should stop trying to do that. – GL2014 Oct 27 '17 at 15:18
  • Doesn’t have to be implementing a kernel, she/he could be writing an emulator / hypervisor as well. – GL2014 Dec 24 '21 at 14:03

3 Answers3

124

A TLB (Translation Lookaside Buffer) is a cache of the translations from virtual memory addresses to physical memory addresses. When a processor changes the virtual-to-physical mapping of an address, it needs to tell the other processors to invalidate that mapping in their caches.

That process is called a "TLB shootdown".

Shahbaz
  • 46,337
  • 19
  • 116
  • 182
Gabe
  • 84,912
  • 12
  • 139
  • 238
80

A quick example:

  1. You have some memory shared by all of the processors in your system.

  2. One of your processors restricts access to a page of that shared memory.

  3. Now, all of the processors have to flush their TLBs, so that the ones that were allowed to access that page can't do so any more.

The actions of one processor causing the TLBs to be flushed on other processors is what is called a TLB shootdown.

Peter Mortensen
  • 30,738
  • 21
  • 105
  • 131
Carl Norum
  • 219,201
  • 40
  • 422
  • 469
19

I think the question demands a more detailed answer.

page table: a data structure that stores the mapping between virtual memory (software) and physical memory (hardware)

however, the page table can be quite large and traversing the page table (to find the virtual address's corresponding physical address) can be a time consuming process. To make this process faster, a cache called the TLB (Translation Lookaside Buffer) is used, which stores the recently accessed virtual memory addresses.

As can be clearly seen the TLB entries need to be in sync with their respective page table entries at all times. Now the TLBs are a per-core cache ie. every core has its own TLB.

Whenever a page table entry is modified by any of the cores, that particular TLB entry is invalidated in all of the cores. This process is called TLB shootdown.

TLB flushing can be triggered by various virtual memory operations that change the page table entries like page migration, freeing pages etc.

coda
  • 2,188
  • 2
  • 22
  • 26
  • 4
    *that particular TLB entry is invalidated in all of the cores* ... by the OS. The hardware doesn't do this automatically; the kernel has to send inter-processor interrupts or otherwise signal the kernel on other cores if they're currently running tasks that use the page table it just modified. But x86 at least doesn't do negative caching, so mapping new memory (changing a PTE from invalid to valid) doesn't need to run any `invlpg` instructions. Remapping or unmapping do need invalidation to stop cores from using the no-longer-valid TLB entry. – Peter Cordes May 11 '18 at 05:20