In 'Computer Organization and Design' RISC-V version ebook by Patterson and Hennessy p850, it says:
A common alternative is to extend the virtual address space by adding a process identifier or task identifier. The Intrinsity FastMATH has an 8-bit address space ID (ASID) field for this purpose. This small field identifies the currently running process; it is kept in a register loaded by the operating system when it switches processes. RISC-V also offers ASID to reduce TLB flushes on context switches. The process identifier is concatenated to the tag portion of the TLB, so that a TLB hit occurs only if both the page number and the process identifier match. This combination eliminates the need to clear the TLB, except on rare occasions.
So what is the rare occasions? Does it refers to the rare condition that the TLB is full of translation cache of one process ? Or something else ?