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I am trying to understand how autodependency is generated in makefiles in the given link, i cannot understand the following piece of code:

DEPDIR = .deps
df = $(DEPDIR)/$(*F)

SRCS = foo.c bar.c ...

%.o : %.c
        @$(MAKEDEPEND); \
          cp $(df).d $(df).P; \
          sed -e 's/#.*//' -e 's/^[^:]*: *//' -e 's/ *\\$$//' \
              -e '/^$$/ d' -e 's/$$/ :/' < $(df).d >> $(df).P; \
          rm -f $(df).d
        $(COMPILE.c) -o $@ $<

-include $(SRCS:%.c=$(DEPDIR)/%.P)

I got it from this link. I know it will generate dependency files but I am not able to understand what this line does:

sed -e 's/#.*//' -e 's/^[^:]*: *//' -e 's/ *\\$$//' \
    -e '/^$$/ d' -e 's/$$/ :/' < $(df).d >> $(df).P; \

Can somebody please explain me this code, so many wildcards give me butterflies, i am new to makefiles.

DarthSpeedious
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2 Answers2

2

That is a number of distinct commands so break it up.

  1. -e 's/#.*//'

    Delete everything that starts with a # (Comments? Pre-processor directives?)

  2. -e 's/^[^:]*: *//'

    Delete everything up to a : on any that has : it.

  3. -e 's/ *\\$$//'

    Delete line-continuation slashes (and spaces before them) from the end of lines.

  4. -e '/^$$/ d'

    Delete any blank lines.

  5. -e 's/$$/ :/'

    Add : to the end of every line.

This adds explicit targets for every listed dependency file so that make "knows" how to build them to avoid the "No rule to make target" errors. The reasoning here is explained in your link in an earlier section.

Briefly, this creates a .P file with the original prerequisites list, then adds targets to it by taking each line, removing any existing target information and any line continuation (\) characters, then adding a target separator (:) to the end. This works with the values for MAKEDEPEND I suggest below; it’s possible you will need to modify the translation for other dependency generators you might use.

Community
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Etan Reisner
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  • Thanks a lot, but the codes in contiki makefile is a little different, In the contiki makefiles, instead of `cp $(df).d $(df).P;` there is `cp $(@:.o=.d) $(@:.o=.$$$$);`. The first one just copies the dependency files into a .P format, but what does the second code do? It would be great if you could help me with it. – DarthSpeedious Jun 06 '15 at 08:52
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    `$(@:.o=.d)` expands to the value of `$@` with a trailing `.o` replaced with `.d`. Similarly `$(@:.o=.$$$$)` expands to the value of `$@` with trailing `.o` replaced with `.$$` (which the shell then expands to the current shell's PID). That's a temporary file presumably used during that rule to avoid over-writing the target file until the process is finished (atomic update). – Etan Reisner Jun 08 '15 at 17:16
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This is not meant to be an answer to your actual question, but since you said you were new to GNU make, I think spreading the words that a simpler way to handle auto dependencies exists won't do any harm.

Nowadays compilers like GCC or Clang can do this for you while compiling your code !

Simply pass them a preprocessor flag:

# Preprocessor flags
CPPFLAGS += -MMD

And include the generated files into the Makefile:

-include $(wildcard *.d)

And you're done.

You can learn more about the preprocessor options here for GCC, Clang simply mirror these options.

A relatively good example lies here too.

Chnossos
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