Questions tagged [multiple-makefiles]
50 questions
13
votes
2 answers
Calling make from within a makefile
I have a Makefile which works perfectly called from a new shell, i.e.:
make -C /dir/
However, if I call this Makefile from another Makefile, it fails due to some complicated dependency issues. Make clearly has knowledge of the nested calls, evident…

user593062
- 1,593
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6
votes
2 answers
Make failure in subdirectory make not stopping build
I have a setup where make is going through a bunch of subdirectories and making inside those directories. I would like it to stop the build on a failure immediately. The code snippet below illustrates this. Can someone point me in the right…

Stephen Burke
- 882
- 3
- 10
- 25
5
votes
1 answer
Multi directory makefile for project
This is how my directory looks like:
/project
makefile
/ceda_lib
makefile
files....
/general
makefile
files....
/CLI
makefile
files....
/objects
files.o
Makefile(main):
1…

alienCY
- 225
- 2
- 12
4
votes
3 answers
How do I check dependencies when invoking a sub-make to build when there are changes?
If I have a makefile that calls another makefile, how to I get the master makefile to correctly check if the dependencies of the subordinate makefile have changed?
For example, if I have the rule
server:
@cd $(SERVERDIR) && $(MAKE)
That…

Zxaos
- 7,791
- 12
- 47
- 61
4
votes
2 answers
Is there a Make debugger? I need to figure out someone else's makefile
I need to add some capabilities to very complex, multi-layered makefile (lots of include files, lots of targets, lots of variables) that was written by someone else who of course is no longer with the company. There are some folks here who…

SDGator
- 2,027
- 3
- 21
- 25
4
votes
2 answers
Installing WordNet on Linux (Ubuntu trusty)
I am trying to install WordNet-3.0 on Ubuntu trusty.
When I ran configure script, I got:
checking for Tcl configuration... configure: WARNING: Can't find Tcl
configuration definitions
It's a warning, but still, configuration stopped without…

Alexandre Holden Daly
- 6,944
- 5
- 25
- 36
3
votes
1 answer
A different make file for each architecture - Android NDK
I'm targeting more than 1 architecture with my c/c++ code compiled with the NDK, the problem is that i need to have a clear organization about my make files, i also have to set the same environment variable differently based on what architecture NDK…

user827992
- 1,743
- 13
- 25
2
votes
2 answers
How to make a single makefile that applies the same command to sub-directories?
For clarity, I am running this on windows with GnuWin32 make.
I have a set of directories with markdown files in at several different levels - theoretically they could be in the branch nodes, but I think currently they are only in the leaf nodes. I…

Vecna
- 47
- 5
2
votes
2 answers
Randomize Parallel Recipe Execution Order In Makefile
I have a makefile that has a ton of subsystem and am able to build it with the -j flag so that it goes much faster and builds the different recipes in parallel.
This seems to be working fine for now but am not sure if I am missing some needed…

Daniel H
- 25
- 3
2
votes
1 answer
Parallel Make - Sub-Projects called multiple times
The question is already answered on file-level. But I have a bigger project which has quite a lot of inter-project-dependencies (caused by DBus headers, which were generated dynamically).
I ve created the following example (example files as ZIP -…

Charly
- 1,270
- 19
- 42
2
votes
2 answers
Autodependency generation in makefiles
I am trying to understand how autodependency is generated in makefiles in the given link, i cannot understand the following piece of code:
DEPDIR = .deps
df = $(DEPDIR)/$(*F)
SRCS = foo.c bar.c ...
%.o : %.c
@$(MAKEDEPEND); \
cp…

DarthSpeedious
- 965
- 1
- 13
- 25
2
votes
2 answers
"heritage" in Makefile
I'm looking a way to overload parts of a Makefile A to another one B, hence extending A.
For instance we have the following makefile A:
TEXT="AHAHA"
default: after-default
before-default:
echo "BEFORE DEFAULT"
default: before-default
…

Kartoch
- 7,610
- 9
- 40
- 68
2
votes
1 answer
How to Overwrite a variable in makefile from terminal
I have created a simple makefile i.e.
COMMON=hello
all:
gcc $(COMMON).c -o $(COMMON).o
The directory in which I am running the makefile contains three files: hello.c add.c multiply.c factorial.c and subtraction.c.
When I am compiling this in the…

user1511590
- 71
- 2
- 5
1
vote
2 answers
Create multiple excel files keeping only specific values in column A from a master sheet
I am really struggling in creating a macro that from a master Excel file creates multiple Excel files based on the values in the first column. More specifically, I have in column "A" some categories, and based on all the categories (ITT1, ITT2,…

Stefano Piacente
- 25
- 2
1
vote
0 answers
Makefile handling auto-generated source and Makefile
I have a problem with a Makefile that's using an auto-generated Makefile to compile .o files from auto-generated .c and .s (assembler) source files.
The context is embedded programming for STM32 microcontrollers, where a Makefile and hardware…

lug_wrench
- 33
- 5