VHDL OR logic with 32 bit vector

Question

zero <= result_i(31) OR result_i(30) OR result_i(29) OR result_i(28)
        OR result_i(27) OR result_i(26) OR result_i(25) OR result_i(24)
        OR result_i(23) OR result_i(22) OR result_i(21) OR result_i(20)
        OR result_i(19) OR result_i(18) OR result_i(17) OR result_i(16)
        OR result_i(15) OR result_i(14) OR result_i(13) OR result_i(12)
        OR result_i(11) OR result_i(10) OR result_i(9) OR result_i(8)
        OR result_i(7) OR result_i(6) OR result_i(5) OR result_i(4)
        OR result_i(3) OR result_i(2) OR result_i(1) OR result_i(0);

How can I make this shorter?

Do you have an example of what you want it to look like? What about anything you've tried? — stevieb, Jun 14 '15 at 03:20
I just want the same logic but shorter. I have tried this: zero <= '0' when result_i = x"00000000" else '1'; — VHDL_, Jun 14 '15 at 03:54
I think this is what you want, but for or operators. http://stackoverflow.com/questions/20296276/and-all-elements-of-an-n-bit-array-in-vhdl — Travis, Jun 14 '15 at 04:56
It depends on how result_i is declared and whether or not you have an IEEE Std 1076-2008 compliant synthesis tool. If the later then there is a single argument OR operator available (zero <= not or result_i; - zero is true when no bits of result_i are set). Various packages have reduction logical operators (e.g. Synopsys std_logic_misc zero <= not or_reduce(result_i);) that do the same thing, as function calls. There's also concurrent assignment (zero <= '1' when result_i = (others => '0') else '0';). There's an if statement equivalent. — , Jun 14 '15 at 04:57
You do realise the shorter alternative you tried does the exact opposite, don't you? — , Jun 14 '15 at 19:01
Does VHDL allow lines to be continued, or do you have to have such a very long line that's hard for anyone to read because it just keeps going on and on and on... — John Saunders, Jun 15 '15 at 07:05

score 3 · Answer 1 · answered Jun 14 '15 at 05:00

I am assuming you are using std_logic/std_logic_vector types. Then you can use or_reduce from ieee.std_logic_misc.

library ieee;
use ieee.std_logic_misc.or_reduce;
...
zero <= or_reduce(result_i);

Or write your own function:

function or_reduce(vector : std_logic_vector) return std_logic is
    variable result : std_logic := '0';
begin
    for i in vector'range loop
        result := result or vector(i);
    end loop
    return result;
end function;

A general tip if you are just starting out with VHDL is to not forget about functions and procedures. Unlike Verilog (Without SystemVerilog) VHDL has good support for writing clean and high level code, even for synthesis, using functions and procedures. If you are doing something repetitive it is a sure sign that it should be wrapped in a function/procedure. In this case there already was a standard function ready to be used though.

You might also want to consider pipelining the or-reduction and inserting flip-flops between the stages. Maybe the 32-bit reduction that you use in your example should still run a reasonably high frequency in an FPGA device but if you are going to use more bits or target a really high frequency you might want to use an or-tree where no more than 6-8 bits are or:ed in each pipeline stage. You can still re-use the or_reduce function for the intermediate operations though.

score 0 · Answer 2 · answered Feb 14 '20 at 15:01

0

You can achieve it with vhdl revision 2008

VHDL-2008 defines unary operators, like these:

outp <= and "11011";

outp <= xor "11011";

So in your case it would be:

zero <= or result_i;

answered Feb 14 '20 at 15:01

Clement

61
6

VHDL OR logic with 32 bit vector

2 Answers2