Verilog Vector Packing/Unpacking Macro

Question

I'm currently grappling with the problem that verilog modules only accept one-dimensional packed vectors as inputs/outputs. For example:

wire [bitWidth-1:0] data;

What I want to do is input a two-dimensional vector with one dimension packed (think array of numbers). For example:

wire [bitWidth-1:0] data [0:numData-1];

I currently have a couple of handy macros that flatten the two-dimensional vector and unflatten a one-dimensional vector. They are:

`define PACK_ARRAY(PK_WIDTH,PK_LEN,PK_SRC,PK_DEST) \
genvar pk_idx; \
generate \
    for (pk_idx=0; pk_idx<(PK_LEN); pk_idx=pk_idx+1) begin : packLoop \
        assign PK_DEST[((PK_WIDTH)*pk_idx+((PK_WIDTH)-1)):((PK_WIDTH)*pk_idx)] = PK_SRC[pk_idx][((PK_WIDTH)-1):0]; \
    end \
endgenerate

`define UNPACK_ARRAY(PK_WIDTH,PK_LEN,PK_DEST,PK_SRC) \
genvar unpk_idx; \
generate \
    for (unpk_idx=0; unpk_idx<(PK_LEN); unpk_idx=unpk_idx+1) begin : unpackLoop \
        assign PK_DEST[unpk_idx][((PK_WIDTH)-1):0] = PK_SRC[((PK_WIDTH)*unpk_idx+(PK_WIDTH-1)):((PK_WIDTH)*unpk_idx)]; \
    end \
endgenerate

These work great if I am only using them to deal with one output and one input to the module I am working in. The problem is that if I use either of these macros more than once in a given module then the following errors occur:

1) The genvars have already been declared. 2) The loop labels have already been used.

I can get around the genvar issue by not declaring it in the macro and declaring it elsewhere, but I can't figure out how to solve the loop label issue and still be able to use a macro to keep clean code.

Any suggestions (except 'switch to system verilog' :P) are welcome! Thanks.

Greg · Accepted Answer · 2017-12-18T21:00:03.370

2

For a pure verilog solution you need to are one more argument for the genvar identifier. Example (Note: replaced ((PK_WIDTH)*unpk_idx+(PK_WIDTH-1)):((PK_WIDTH)*unpk_idx) with (PK_WIDTH)*unpk_idx +: PK_WIDTH for simplicity, see here & here ):

`define UNPACK_ARRAY(PK_WIDTH,PK_LEN,PK_DEST,PK_SRC,UNPK_IDX) \
genvar UNPK_IDX; \
generate \
  for (UNPK_IDX=0; UNPK_IDX<(PK_LEN); UNPK_IDX=UNPK_IDX+1) begin //: unpackLoop <-- remove label\
    assign PK_DEST[UNPK_IDX][((PK_WIDTH)-1):0] = PK_SRC[(PK_WIDTH)*unpk_idx +: PK_WIDTH]; \
  end \
endgenerate

There is a simpler solution if SystemVerilog is an option using the streaming operators. See IEEE Std 1800-2012 § 11.4.14 Streaming operators (pack/unpack). Example:

// packing
assign packed_array = {>>{unpacked_array}};
// unpacking
assign unpacked_array = {<<PK_WIDTH{packed_array}};

edited Dec 18 '17 at 21:00

answered Jun 23 '15 at 18:31

Greg

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Thanks for the help. Will definitely implement the ``genvar`` parameter. Do you have any suggestions on how to solve the ``generate`` loop label issue? – mitch Jun 23 '15 at 18:50
While I like the stream operator for doing some things (especial bit reordering), many synthesis tools dont support it yet :( – Unn Jun 23 '15 at 18:50
@mitch Can you not use a macro argument for the label as well? – Unn Jun 23 '15 at 18:51
1

You can remove the label name as well. Just let it auto name – Greg Jun 23 '15 at 18:53
If you can use an argument for the label, I can't figure it out. Also, how can you just remove the label? I'm using Quartus 13.0sp1 and verilog 2001 I think. – mitch Jun 23 '15 at 18:57
UPDATE: Yes, you can use a macro argument for the label as well. Just add the extra argument and replace the label with the argument verbatim. My screwup what that I was putting brackets around the label. – mitch Jun 23 '15 at 19:24
Quartus 13.0 supports SystemVerilog if you want to make things easier (unless theres some other constraint). @Greg Ive had experience where tools refuse to autoname for loops in generate statements and fail without explicit labels, so it depends – Unn Jun 23 '15 at 20:12
@mitch, I commented out the label name in my answer, delete might be better in your actual code. – Greg Jun 23 '15 at 20:12

Verilog Vector Packing/Unpacking Macro

1 Answers1