Error: is not a constant

Question

module concat(
    input [7:0] data_in,
    input rst,
    input clk,
    output reg[127:0] data_out,
    output reg valid_out
    );

    integer i;

    reg[127:0] datatemp=0;

always@(data_in)
begin
    if(rst)
    begin
        data_out<=0;
        datatemp<=0;
    end
    else
    begin
    for(i=0;i<=127;i=i+8)
    begin
        datatemp[i:i+7]<=data_in;
    end
        if(i==127)
        begin
            valid_out<=1;
            data_out<=datatemp;
        end
    end
end


endmodule

This code is showing the following error:

Line 44: i is not a constant

Please tell me how to remove it. I'd be really grateful.

If you ask questions here, do not use phrases like "Please reply ASAP". This makes you look as if you feel entitled to an answer. People on this site help others for free, we are not paid service workers. If your post looks unfriendly or demanding you won't get any answers. Also please post the language, compiler and platform that you are using. I tagged it for Verilog, since it looks like Verilog. And please mark the line that results in the error. The code you posted is less than 44 lines long. — Dakkaron, Jun 25 '15 at 10:09
possible duplicate of [Verilog: "... is not a constant"](http://stackoverflow.com/questions/29815974/verilog-is-not-a-constant) — Qiu, Jun 25 '15 at 16:55

Russell · Answer 1 · 2016-01-13T18:57:39.187

It looks like you ended your for loop too soon. You are checking the value of i for it being equal to 127 after the for loop is done. I think for your code to compile you want this:

for(i=0;i<=127;i=i+8)
begin
    datatemp[i:i+7]<=data_in;
    if(i==127)
    begin
        valid_out<=1;
        data_out<=datatemp;
    end
end

But are you sure that this will do what you want it to do? Do you understand that in Verilog for-loops are unrolled? They are very different for how they behave in C or Java or any software language. I'm not sure why you would ever need to check the value of i, unless you were not understanding how for-loops work in Synthesizable Verilog.

Error: is not a constant

1 Answers1