Verilog : Muliplication of Integer and parameter and for loop

Question

When i am trying to compile following verilog RTL cadence simulator is throwing a error as illegal operand for constant expression.

RTL is:

module selection_logic( data_out, data_in , valid_info);

input  [(number_of_channel * per_channel_data) - 1 : 0] data_in;
input  [number_of_channel - 1: 0] valid_info;

output reg [number_of_channel - 1 : 0] data_in;


integer i;

always @(*)
begin
for (i = 0; i < number_of_channel; i = i + 1)
begin
if (valid_info[i])
data_out[(per_channel_data*(i+1)) - 1: per_channel_data*i] = data_in[[(per_channel_data*(i+1)) - 1: per_channel_data*i] 

else
data_out[(per_channel_data*(i+1)) - 1: per_channel_data*i] = {per_channel_data{1'b0};
end
end


endmodule

score 0 · Answer 1 · edited May 23 '17 at 12:29

Array slicing using the arrayName[MSB:LSB] require MSB and LSB to be constants. Instead, use the arrayName[start_bit +: WIDTH], where WIDTH is a constant and start_bit can be a variable. Refer to "Indexing vectors and arrays with +:" and "What is `+:` and `-:`?"

data_out[per_channel_data*i +: per_channel_data] = data_in[per_channel_data*i +: per_channel_data];

If stuck with with Verilog-1995, then add a second for-loop and assign each bit individually:

for(i=0; i<per_channel_data; i=i+1) begin
  for(j=0; j<per_channel_data; j=j+1) begin
    if (valid_info[i])
      data_out[per_channel_data*i+j] = data_in[per_channel_data*i+j];
    else
      data_out[per_channel_data*i+j] = 1'b0;
  end
end

Verilog : Muliplication of Integer and parameter and for loop

1 Answers1