What is the difference between "wait until rising_edge(clk)" vs "if rising_edge(clk)"?

Question

I came across two styles of process statements in VHDL.

process(clk)
begin
    if rising_edge(clk)
...do something...

The other one is

process
begin
    wait until rising_edge(clk)
    ...do something...

What are the pros and cons of each method?

Closely related - [clk'event vs rising_edge()](https://stackoverflow.com/q/15205202). — Henke, Apr 05 '21 at 13:55
An answer is the subject of [a meta question](https://meta.stackoverflow.com/questions/418652/should-we-not-flag-rude-abusive-a-post-containing-valuable-content#comment914681_418652). — Peter Mortensen, Jun 19 '22 at 16:55

wap26 · Accepted Answer · 2015-09-22T12:46:16.260

3

Assuming the ... part of the second example does not have any wait statement, the two forms are semantically equivalent.

They will behave identically in simulation.

However, the first form is the recommended style for synthesis and will be deemed more readable by many.

edited Sep 22 '15 at 12:46

answered Sep 22 '15 at 12:40

wap26

2,180
1
17
32

2

Recommended by whom? Both forms are supported, see the withdrawn IEEE Std 1076.6-2004, 6.1.3.1 Edge-sensitive storage from a process with sensitivity list and one clock and 6.1.3.2 Edge-sensitive storage using a single wait statement. The distinction is whether or not the process has a sensitivity list which implies `wait on clk;` as the last sequential statement of a process (IEEE Std 1076-2008 11.3 Process statement). Which form is pure coding style choice., – Sep 22 '15 at 20:00
@user I don't have any reference at hand, but there are _synthesis_ tools which won't infer a proper FF with the `wait` syntax. – wap26 Sep 23 '15 at 07:29
And they wouldn't have been 1076.6 compliant. – Sep 23 '15 at 08:09
@user Yes, but synthesis tools are not meant to implement the complete standard anyway. – wap26 Sep 23 '15 at 08:19
IEEE Std 1076.6-2004 1.2.2 Tool compliance 1.2.2 Tool compliance A synthesis tool shall be defined as being compliant to this standard if it a) Accepts ***all*** models that adhere to the model compliance definition defined in 1.2.1. 1.2.1 Model compliance A VHDL model shall be defined as being compliant to this standard if the model a) Uses only constructs described as supported or ignored in this standard b) Adheres to the semantics defined in this standard – Sep 23 '15 at 08:33
@user Fine, you're right. Yet, doc for Altera Quartus II recommends the sensitivity list style for synchronous processes. Why do they recommend a specific style although they support both, I don't know. – wap26 Sep 23 '15 at 08:37
3

@Wap26 They are not 100% equivalent: according the LRM the sensitivity list is equivalent to the same process without the sensitivity list and with a `wait on ;` added as the **last** statement of the process, not first. So, you are only almost right that they are equivalent: during simulation the initialization is different. Depending on the `...` the difference might be observable or not. – Renaud Pacalet Sep 23 '15 at 09:42
@Renaud, right but here we added the `if rising_edge(clk)` in the version with the sensitivity list, so neither `…do something` parts will be run during initialization. – wap26 Sep 23 '15 at 10:06
@wap26 ...except if there is something after the corresponding `end if;` This is why a added this comment. The question is not detailed enough to be sure that the two codes are equivalent. – Renaud Pacalet Sep 23 '15 at 10:32

score 2 · Answer 2 · edited Jun 19 '22 at 16:45

2

Both forms are equivalent for synthesis in Vivado. The second wait form can be considered more compact as it "saves" an indentation level.

edited Jun 19 '22 at 16:45

Peter Mortensen

30,738
21
105
131

answered Sep 22 '15 at 15:36

kraigher

629
4
9

IMHO, saving indentation level is pointless, unless your editor only displays 80 columns. – wap26 Sep 23 '15 at 07:31
I am not saying it has huge value. The choice is mostly arbitrary and down to personal preference like any coding standard. The tools do not care. – kraigher Sep 23 '15 at 08:18
Additionally, if your text editor or IDE does "fold" the code, then the `wait until ...` will be hidden, but a synthesis list would still be visible, assuming it is on the same line as the process keyword. – andrsmllr Jul 23 '19 at 12:09

score 0 · Answer 3 · edited Jun 19 '22 at 16:48

I generally agree with wap26's answer, with one addition.

I sometimes like to write a top-level architecture which acts as both the synthesisable top-level design and as the simulation test bench - typically for smaller designs.

Within such designs, you often drive the clock yourself during simulation, using wait statements, like:

if IS_SIMULATION then
    wait for SIM_CLK_PERIOD / 2; 
    clk <= '0';
    wait for SIM_CLK_PERIOD / 2;
    clk <= '1';
else
    clk <= external_clk;
end if;

The issue now is that you still need to handle the initial/reset state for the synthesisable section. This requires an assertion that the entity's signals have been initialised before the first (or some) rising edge of the external clock.

But we can't use if rising_edge(external_clk), because this process cannot have a sensitivity list (it uses wait statements in the simulation section). Therefore, in this case, using wait until rising_edge(external_clk) is required.

score -1 · Answer 4 · edited Jun 11 '22 at 16:19

A if [conditions].... : continuously execute the acts. The process will go on regardless of whether the conditions is met or not, only skipping the statement in the "if" when not meeting the conditions, and will execute the afterwards statements, in all weather!

B wait until [conditions]... : only execute the acts at the conditions met! If the conditions are not met, the process will hang (or be blocked/suspended) here, and can't go on, even there have many statements afterwards.

In most cases, expecially in simulations, B is better than A. In some cases, only B can be done, rather than A.

Here's an example:

A

for i in 0 to 10 loop;
  if rising_edge(clk) then
     ..acts..
  end if;    
end loop;

B

 for i in 0 to 10 loop;
  wait until rising_edge(clk);
     ...acts....    
   end loop;

A can't work, but B can!

score -3 · Answer 5 · edited Jun 19 '22 at 16:43

-3

Essentially, the second type is only useful in simulation. The wait statement requires time to flow between separate statements within a process, which is unlike the hardware synthesis process. It will typically appear within a simulation stimulus or diagnostic process.

In the first form, the process is triggered by the clock event and runs in a single step, representing synchronous logic.

edited Jun 19 '22 at 16:43

Peter Mortensen

30,738
21
105
131

answered Sep 22 '15 at 12:41

Yann Vernier

15,414
2
28
26

2

I do not fully agree with the second part of your answer. The `wait` can indeed be used to produce complex / asynchronous stimuli, but it can also be used to model a completely synchronous behavior, a flip-flop for instance. – wap26 Sep 22 '15 at 12:45
2

This is incorrect. In terms of "time flow", the two are essentially identical, with only one minor (irrelevant) difference between the two. I would expect most synthesis tools, if not all, to accept both forms. Almost everybody uses the first, though. – EML Sep 22 '15 at 13:38
1

You are misinformed. In a previous project we used `wait until rising_edge(clk)` since it "saved" an indentation level and was more compact. A synthesis tool such as for example Vivado considers both forms equivalent. – kraigher Sep 22 '15 at 15:34

What is the difference between "wait until rising_edge(clk)" vs "if rising_edge(clk)"?

5 Answers5

Linked