1

In a VCD file I would like to specify that some events occurred at a particular time. To that end, I tried to define a single bit signal which value is almost the time 0, and switching this value to 0 and then back to 1 in the same time (at the time when my event occurs). Unfortunately nothing is displayed when looking into the file with gtkwave. How could I achieve this behavior ?

Manuel Selva
  • 18,554
  • 22
  • 89
  • 134
  • 1
    If you flip a signal without advancing time does this even get written to the VCD? I would expect the signal to be either 0 or 1 or x but not to be able to see it go to 1 and back. – dave Oct 13 '15 at 05:53
  • @dave I am generating a VCD file myself, so yes I can switch it on and off on the same time. Moreover, to my understanding the VCD file MUST be time ordered, do you confirm that ? – Manuel Selva Oct 13 '15 at 06:02
  • I still wouldn't expect it to show up in gtkwave: the VCD doesn't make sense .... a signal can't have two values at the same time. – dave Oct 13 '15 at 06:04
  • Ok thank you for clear answer. So do you think there is a mean to show an "instantaneous" event in a VCD file ? – Manuel Selva Oct 13 '15 at 06:06
  • 1
    No there isn't but you could use a time interval that is less than your other time intervals (e.g. some small fraction of the clock) – dave Oct 13 '15 at 06:07
  • Ok thank you again. To do that I would have to set a time resolution lower than my clock cycle. – Manuel Selva Oct 13 '15 at 06:20

1 Answers1

2

Use event as your variable data type and use -> to force an event on it. It will show up in gtkwave as an impulse arrow in zero time. No tricks with timescales are necessary.

Tony Bybell
  • 159
  • 1
  • 2
  • Thank you, this is exactly what I was looking for ! Neverthless, I am not able to find the right syntax to raise the event at a particular time (event definition is correct), can you please show an exemple ? Also, is there any definitive documentation of the VCD file format ? – Manuel Selva Oct 14 '15 at 08:04
  • Here's an example: module top; event a; initial begin $dumpfile("whatever.vcd"); $dumpvars(0, top); #10 ->a; #10 ->a; #10 ->a; #10 ->a; #10 ->a; end endmodule – Tony Bybell Oct 14 '15 at 19:51
  • For VCD syntax, you can look in the Verilog spec. – Tony Bybell Oct 14 '15 at 19:54